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Total properties:
36
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Patent #:
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Issue Dt:
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06/20/1995
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Application #:
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07928552
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Filing Dt:
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08/11/1992
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Title:
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MEMORY CONTROLLER AND METHOD DETERMINING EMPTY/FULL STATUS OF A FIFO MEMORY USING GRAY CODE COUNTERS
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Patent #:
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Issue Dt:
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04/22/1997
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Application #:
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08448003
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Filing Dt:
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05/23/1995
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Title:
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RESOURCE ALLOCATION WITH PARAMETER COUNTER IN MULTIPLE REQUESTER SYSTEM
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Patent #:
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Issue Dt:
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02/17/1998
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Application #:
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08489489
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Filing Dt:
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06/12/1995
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Title:
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PARTITIONED DECOMPRESSION OF AUDIO DATA USING AUDIO DECODER ENGINE FOR COMPUTATIONALLY INTENSIVE PROCESSING
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Patent #:
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Issue Dt:
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10/07/1997
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Application #:
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08576872
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Filing Dt:
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12/21/1995
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Title:
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GRAPHICS DISPLAY SYSTEM WITH A LOW LEVEL HARDWARE DEPENDENT GRAPHICS LIBRARY
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Patent #:
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Issue Dt:
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05/05/1998
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Application #:
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08612691
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Filing Dt:
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03/08/1996
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Title:
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SIGMA-DELTA DIGITAL-TO-ANALOG CONVERSION SYSTEM AND PROCESS THROUGH RECONSTRUCTION AND RESAMPLING
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Patent #:
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Issue Dt:
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01/19/1999
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Application #:
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08616835
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Filing Dt:
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03/15/1996
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Title:
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MIXED VOLTAGE, MULTI-RAIL, HIGH DRIVE, LOW NOISE, ADJUSTABLE SLEW INPUT/OUTPUT BUFFER
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Patent #:
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Issue Dt:
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05/25/1999
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Application #:
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08801002
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Filing Dt:
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02/19/1997
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Title:
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VOLTAGE TOLERANT INPUT/OUTPUT BUFFER
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|
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Patent #:
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Issue Dt:
|
02/23/1999
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Application #:
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08813343
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Filing Dt:
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03/07/1997
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Title:
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TRANSFORMERLESS DATA ACCESS ARRANGEMENT
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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08899355
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Filing Dt:
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07/23/1997
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Title:
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METHOD OF EMBEDDING PAGE ADDRESS TRANSLATION ENTRIES WITHIN A SEQUENTIALLY ACCESSED DIGITAL AUDIO DATA STREAM
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Patent #:
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Issue Dt:
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05/11/1999
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Application #:
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08900084
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Filing Dt:
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07/24/1997
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Title:
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VOLTAGE TOLERANT BUS HOLD LATCH
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Patent #:
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Issue Dt:
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10/12/1999
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Application #:
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08926174
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Filing Dt:
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09/09/1997
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Title:
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SYSTEM AND METHOD FOR A MIXED VOLTAGE DRIVE SYSTEM FOR FLOATING SUBSTRATE TECHNOLOGY
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Patent #:
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Issue Dt:
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04/20/1999
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Application #:
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08956710
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Filing Dt:
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10/23/1997
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Title:
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MULTIPLE-PORT RING BUFFER
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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08974073
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Filing Dt:
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11/19/1997
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Title:
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VOLTAGE TOLERANT BUFFER
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|
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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08991392
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Filing Dt:
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12/16/1997
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Title:
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PROCESSOR HAVING MULTIPLE DATAPATH INSTANCES
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|
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Patent #:
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|
Issue Dt:
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03/21/2000
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Application #:
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09005077
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Filing Dt:
|
01/09/1998
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Title:
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OUTPUT BUFFER CIRCUIT AND METHOD THAT COMPENSATE FOR OPERATING CONDITIONS AND MANUFACTURING PROCESSES
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Patent #:
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|
Issue Dt:
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01/16/2001
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Application #:
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09020152
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Filing Dt:
|
02/06/1998
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Title:
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FAST ADDER/SUBTRACTOR FOR SIGNED FLOATING POINT NUMBERS
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|
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Patent #:
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|
Issue Dt:
|
07/04/2000
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Application #:
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09039283
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Filing Dt:
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03/12/1998
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Title:
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MULTIPLE MODE ANALOG JOYSTICK INTERFACE
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|
|
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09039973
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Filing Dt:
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03/16/1998
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Publication #:
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Pub Dt:
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12/13/2001
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Title:
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MODIFYING CIRCUIT DESIGNS RUNNING FROM BOTH EDGES OF CLOCK TO RUN FROM POSITIVE DESIGNS RUNNING FROM BOTH EDGES OF CLOCK TO RUN FROM POSITIVE EDGE
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Patent #:
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|
Issue Dt:
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12/21/1999
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Application #:
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09053555
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Filing Dt:
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04/01/1998
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|
Title:
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VOLTAGE LEVEL SHIFT SYSTEM AND METHOD
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Patent #:
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|
Issue Dt:
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12/05/2000
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Application #:
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09075350
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Filing Dt:
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05/08/1998
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Title:
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MULTIPLE INPUT SIGNATURE TESTING & DIAGNOSIS FOR EMBEDDED BLOCKS IN INTEGRATED CIRCUITS
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|
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Patent #:
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|
Issue Dt:
|
06/13/2000
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Application #:
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09088645
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Filing Dt:
|
06/01/1998
|
|
Title:
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TUNABLE DIGITAL OSCILLATOR CIRCUIT AND METHOD FOR PRODUCING CLOCK SIGNALS OF DIFFERENT FREQUENCIES
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Patent #:
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|
Issue Dt:
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05/14/2002
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Application #:
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09088754
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Filing Dt:
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06/02/1998
|
|
Title:
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EDGE-TRIGGERED SCAN FLIP-FLOP AND ONE-PASS SCAN SYNTHESIS METHODOLOGY
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|
|
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Patent #:
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Issue Dt:
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01/02/2001
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Application #:
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09103757
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Filing Dt:
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06/24/1998
|
|
Title:
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EFFICIENT ROUTING FROM MULTIPLE SOURCES TO EMBEDDED DRAM AND OTHER LARGE CIRCUIT BLOCKS
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|
|
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Patent #:
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|
Issue Dt:
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04/03/2001
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Application #:
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09104049
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Filing Dt:
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06/24/1998
|
|
Title:
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HYBRID CIRCUIT MODEL SIMULATOR FOR ACCURATE TIMING AND NOISE ANALYSIS
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/29/2000
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Application #:
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09128220
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Filing Dt:
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08/03/1998
|
|
Title:
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SYSTEM AND METHOD FOR EFFICIENTLY TRANSFERRING INFORMATION BETWEEN PROCESSORS
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|
|
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Patent #:
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|
Issue Dt:
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07/25/2000
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Application #:
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09149549
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Filing Dt:
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09/08/1998
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|
Title:
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VERTICALLY STACKABLE INTEGRATED CIRCUIT
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|
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Patent #:
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|
Issue Dt:
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10/26/1999
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Application #:
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09225650
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Filing Dt:
|
01/05/1999
|
|
Title:
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VOLTAGE TOLERANT INPUT/OUTPUT BUFFER
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|
|
|
|
Patent #:
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|
Issue Dt:
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04/18/2000
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Application #:
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09252638
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Filing Dt:
|
02/19/1999
|
|
Title:
|
MULTIPLE-PORT RING BUFFER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/14/2001
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Application #:
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09285320
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Filing Dt:
|
04/02/1999
|
|
Title:
|
DIFFERENTIAL CHARGE PUMP WITH LOW VOLTAGE COMMON MODE FEEDBACK CIRCUIT
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|
|
|
|
Patent #:
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|
Issue Dt:
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05/21/2002
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Application #:
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09320191
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Filing Dt:
|
05/26/1999
|
|
Title:
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SKEW-INDEPENDENT MEMORY ARCHITECTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
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Application #:
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09326161
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Filing Dt:
|
06/04/1999
|
|
Title:
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SINGLE RAIL DOMINO LOGIC FOR FOUR-PHASE CLOCKING SCHEME
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|
|
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Patent #:
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|
Issue Dt:
|
02/11/2003
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Application #:
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09676460
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Filing Dt:
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09/29/2000
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|
Title:
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READ DATA VALID LOOP-BACK FOR HIGH SPEED SYNCHRONIZED DRAM CONTROLLER
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|
|
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Patent #:
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|
Issue Dt:
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03/12/2002
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Application #:
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09729869
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Filing Dt:
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12/05/2000
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|
Title:
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System and method for efficiently implementing a double data rate memory architecture
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|
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09882637
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Filing Dt:
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06/14/2001
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|
Publication #:
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Pub Dt:
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10/18/2001
| | | | |
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Title:
|
DIFFERENTIAL CHARGE PUMP WITH LOW VOLTAGE COMMON MODE FEEDBACK CIRCUIT
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09944936
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Filing Dt:
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08/30/2001
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Publication #:
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Pub Dt:
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03/06/2003
| | | | |
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Title:
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INPUT STAGE APPARATUS AND METHOD HAVING A VARIABLE REFERENCE VOLTAGE
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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29129604
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Filing Dt:
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09/18/2000
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Title:
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Server enclosure
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