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Patent Assignment Details
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Reel/Frame:017336/0712   Pages: 18
Recorded: 03/15/2006
Conveyance: TERMINATION OF SECURITY AGREEMENT
Total properties: 14
1
Patent #:
Issue Dt:
04/11/1995
Application #:
07939895
Filing Dt:
09/02/1992
Title:
GENERAL PURPOSE, HASH-BASED TECHNIQUE FOR SINGLE-PASS LOSSLESS DATA COMPRESSION
2
Patent #:
Issue Dt:
12/26/1995
Application #:
08037893
Filing Dt:
03/26/1993
Title:
FLASH MEMORY MASS STORAGE ARCHITECTURE INCORPORATING WEAR LEVELING TECHNIQUE
3
Patent #:
Issue Dt:
02/07/1995
Application #:
08038668
Filing Dt:
03/26/1993
Title:
FLASH MEMORY MASS STORAGE ARCHITECTURE
4
Patent #:
Issue Dt:
12/05/1995
Application #:
08124938
Filing Dt:
09/21/1993
Title:
PROGRAMMABLE REDUNDANCY/SYNDROME GENERATOR
5
Patent #:
Issue Dt:
01/16/1996
Application #:
08131495
Filing Dt:
10/04/1993
Title:
FLASH MEMORY MASS STORAGE ARCHITECTURE INCORPORATING WEAR LEVELING TECHNIQUE WITHOUT USING CAM CELLS
6
Patent #:
Issue Dt:
06/04/1996
Application #:
08293676
Filing Dt:
08/19/1994
Title:
FAST RECOVERING CHARGE PUMP FOR CONTROLLING A VCO IN A LOW POWER CLOCKING CIRCUIT
7
Patent #:
Issue Dt:
09/10/1996
Application #:
08306918
Filing Dt:
09/16/1994
Title:
MULTIPURPOSE ERROR CORRECTION CALCULATION CIRCUIT
8
Patent #:
Issue Dt:
11/14/1995
Application #:
08325831
Filing Dt:
10/18/1994
Title:
FINITE FIELD INVERSION
9
Patent #:
Issue Dt:
02/25/1997
Application #:
08326884
Filing Dt:
10/21/1994
Title:
METHOD AND APPARATUS FOR COMBINING CONTROLLER FIRMWARE STORAGE AND CONTROLLER LOGIC IN A MASS STORAGE SYSTEM
10
Patent #:
Issue Dt:
09/16/1997
Application #:
08327681
Filing Dt:
10/21/1994
Title:
ERROR CORRECTION METHOD AND APPARATUS FOR DISK DRIVE EMULATOR
11
Patent #:
Issue Dt:
10/06/1998
Application #:
08420239
Filing Dt:
04/11/1995
Title:
HIGH PERFORMANCE METHOD OF AND SYSTEM FOR SELECTING ONE OF A PLURALITY OF IC CHIPS WHILE REQUIRING MINIMAL SELECT LINES
12
Patent #:
Issue Dt:
12/01/1998
Application #:
08509706
Filing Dt:
07/31/1995
Title:
DIRECT LOGICAL BLOCK ADDRESSING FLASH MEMORY MASS STORAGE ARCHITECTURE
13
Patent #:
Issue Dt:
01/21/1997
Application #:
08515188
Filing Dt:
08/15/1995
Title:
A NON-VOLATILE MEMORY SYSTEM OF MULTI-LEVEL TRANSISTOR CELLS AND METHODS USING SAME
14
Patent #:
Issue Dt:
11/10/1998
Application #:
08527484
Filing Dt:
09/13/1995
Title:
METHOD OF AND ARCHITECTURE FOR CONTROLLING SYSTEM DATA WITH AUTOMATIC WEAR LEVELING IN A SEMICONDUCTOR NON-VOLATILE MASS STORAGE MEMORY
Assignor
1
Exec Dt:
07/19/2000
Assignee
1
47421 BAYSIDE PARKWAY
FREMONT, CALIFORNIA 94538
Correspondence name and address
JOHN T. MCNELIS
FENWICH & WEST LLP
SILICON VALLEY CENTER
801 CALIFORNIA STREET
MOUNTAIN VIEW, CA 94041

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