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Total properties:
14
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Patent #:
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Issue Dt:
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12/05/1995
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Application #:
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08287384
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Filing Dt:
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08/08/1994
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Title:
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THERMAL TRENCH ISOLATION
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Patent #:
|
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Issue Dt:
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11/26/1996
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Application #:
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08445664
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Filing Dt:
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05/22/1995
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Title:
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INTEGRATED CIRCUITRY HAVING A THIN FILM POLYSILICON LAYER IN OHMIC CONTACT WITH A CONDUCTIVE LAYER
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Patent #:
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Issue Dt:
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10/28/1997
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Application #:
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08562928
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Filing Dt:
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11/27/1995
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Title:
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SEMICONDUCTOR PROCESSING METHOD OF FORMING A BURIED CONTACT AND CONDUCTIVE LINE
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08566332
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Filing Dt:
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12/01/1995
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Title:
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METHOD OF TRENCH ISOLATION DURING THE FORMATION OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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06/30/1998
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Application #:
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08567916
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Filing Dt:
|
12/06/1995
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Title:
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SEMICONDUCTOR PROCESSING METHOD OF FORMING A BURIED CONTACT
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Patent #:
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|
Issue Dt:
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08/31/1999
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Application #:
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08626278
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Filing Dt:
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04/04/1996
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Title:
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METHOD FOR REDUCING THE HEIGHTS OF INTERCONNECTS ON A PROJECTING REGION WITH A SMALLER REDUCTION IN THE HEIGHTS OF OTHER INTERCONNECTS
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|
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Patent #:
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Issue Dt:
|
05/25/1999
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Application #:
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08774609
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Filing Dt:
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12/30/1996
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Title:
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LEADS UNDER CHIP IN CONVENTIONAL IC PACKAGE
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|
|
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Patent #:
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|
Issue Dt:
|
04/30/2002
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Application #:
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09050218
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Filing Dt:
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03/27/1998
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Publication #:
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Pub Dt:
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12/13/2001
| | | | |
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Title:
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METHODS INCORPORATING DETECTABLE ATOMS INTO ETCHING PROCESSES
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|
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Patent #:
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|
Issue Dt:
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11/27/2001
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Application #:
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09139814
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Filing Dt:
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08/25/1998
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Title:
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METHOD AND APPARATUS FOR ENDPOINTING A CHEMICAL-MECHANICAL PLANARIZATION PROCESS
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09200253
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Filing Dt:
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11/25/1998
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Title:
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DEVICE INCLUDING A CONDUCTIVE LAYER PROTECTED AGAINST OXIDATION
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Patent #:
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|
Issue Dt:
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04/24/2001
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Application #:
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09285668
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Filing Dt:
|
04/05/1999
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Title:
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METHOD OF FORMING A METAL SEED LAYER FOR SUBSEQUENT PLATING
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|
|
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Patent #:
|
|
Issue Dt:
|
12/11/2001
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Application #:
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09286787
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Filing Dt:
|
04/06/1999
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Title:
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CONDUCTIVE MATERIAL FOR INTEGRATED CIRCUIT FABRICATION
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|
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09389535
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Filing Dt:
|
09/02/1999
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|
Title:
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METHOD OF FORMING A CONDUCTIVE SILICIDE LAYER ON A SILICON COMPRISING SUBSTRATE AND METHOD OF FORMING A CONDUCTIVE SILICIDE CONTACT
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|
|
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Patent #:
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|
Issue Dt:
|
12/03/2002
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Application #:
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09753548
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Filing Dt:
|
01/04/2001
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|
Publication #:
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|
Pub Dt:
|
08/09/2001
| | | | |
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Title:
|
METHOD OF FORMING A METAL SEED LAYER FOR SUBSEQUENT PLATING
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|
