Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 007133/0724 | |
| Pages: | 5 |
| | Recorded: | 09/19/1994 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
9
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Patent #:
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Issue Dt:
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02/20/1996
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Application #:
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07726773
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Filing Dt:
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07/08/1991
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Title:
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RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
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Patent #:
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Issue Dt:
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10/05/1993
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Application #:
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07887511
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Filing Dt:
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05/22/1992
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Title:
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LOW-POWER AREA-EFFICIENT ABSOLUTE VALUE ARITHMETIC UNIT
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Patent #:
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Issue Dt:
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05/25/1993
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Application #:
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07897729
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Filing Dt:
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06/12/1992
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Title:
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SYSTEM AND METHOD FOR REDUCING GROUND BOUNCE IN INTEGRATED CIRCUIT OUTPUT BUFFERS
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Patent #:
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Issue Dt:
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08/31/1993
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Application #:
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07948687
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Filing Dt:
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09/22/1992
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Title:
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CROSS-POLARIZATION INTERFERENCE CANCELLER
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Patent #:
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Issue Dt:
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08/29/1995
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Application #:
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07968901
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Filing Dt:
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10/30/1992
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Title:
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POLYGON RASTERIZATION
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Patent #:
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Issue Dt:
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08/08/1995
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Application #:
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07972699
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Filing Dt:
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11/06/1992
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Title:
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SYSTEM AND METHOD FOR SYNCHRONIZING PROCESSORS IN A PARALLEL PROCESSING ENVIRONMENT
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Patent #:
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Issue Dt:
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06/27/1995
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Application #:
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07973344
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Filing Dt:
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11/09/1992
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Title:
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SYSTEM AND METHOD FOR SUPPORTING CONTEXT SWITCHING WITHIN A MULTIPROCESSOR SYSTEM HAVING FUNCTIONAL BLOCKS THAT GENERATE STATE PROGRAMS WITH CODED REGISTER LOAD INSTRUCTIONS
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Patent #:
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Issue Dt:
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03/12/1996
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Application #:
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07997943
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Filing Dt:
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12/31/1992
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Title:
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INPUT OUTPUT CONTROL UNIT HAVING DEDICATED PATHS FOR CONTROLLING THE INPUT AND OUTPUT OF DATA BETWEEN HOST PROCESSOR AND EXTERNAL DEVICE
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Patent #:
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Issue Dt:
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02/18/1997
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Application #:
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07999648
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Filing Dt:
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12/31/1992
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Title:
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SYSTEM AND METHOD FOR ASSIGNING TAGS TO INSTRUCTIONS TO CONTROL INSTRUCTION EXECUTION
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Assignee
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4-1, NISHISHINJUKU 2-CHOME |
SHINJUKU-KU, TOKYO-TO, JAPAN |
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Correspondence name and address
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W. DOUGLAS CAROTHERS, JR.
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S-MOS SYSTEMS, INC.
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2460 NORTH FIRST ST.
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SAN JOSE, CA 95131-1002
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