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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09187691
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Filing Dt:
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11/05/1998
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Title:
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SEMICONDUCTOR-OXIDE-SEMICONDUCTOR CAPACITOR FORMED IN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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01/02/2001
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Application #:
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09188778
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Filing Dt:
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11/09/1998
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Title:
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HIGH VOLTAGE SWITCH FOR PROVIDING VOLTAGES HIGHER THAN 2.5 VOLTS WITH TRANSISTORS MADE USING A 2.5 VOLT PROCESS
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Patent #:
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Issue Dt:
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06/15/1999
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Application #:
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09196080
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Filing Dt:
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11/19/1998
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Title:
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POWER CONVERTER WITH 2.5 VOLT SEMICONDUCTOR PROCESS COMPONENTS
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09196449
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Filing Dt:
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11/19/1998
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Title:
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ENHANCED I/O CONTROL FLEXIBILITY FOR GENERATING CONTROL SIGNALS
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09198653
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Filing Dt:
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11/24/1998
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Title:
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EEPROM DEVICE HAVING IMPROVED DATA RETENTION AND OPERATING METHOD
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09198796
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Filing Dt:
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11/24/1998
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Title:
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VARIABLE SIZED LINE DRIVING AMPLIFIERS FOR INPUT/OUTPUT BLOCKS (IOBS) IN FPGA INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/05/2002
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Application #:
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09199664
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Filing Dt:
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11/25/1998
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Title:
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CLOCK TREE TOPOLOGY
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09200395
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Filing Dt:
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11/24/1998
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Title:
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METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING HIGH RELIABILITY PASSIVATION OVERLYING A MULTI-LEVEL INTERCONNECT
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09201081
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Filing Dt:
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11/30/1998
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Title:
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PHASE LOCKED LOOP WITH A LOCK DETECTOR
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09203149
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Filing Dt:
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12/01/1998
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Publication #:
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Pub Dt:
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10/18/2001
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Title:
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EEPROM CELL WITH TUNNELING ACROSS ENTIRE SEPARATED CHANNELS
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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09207558
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Filing Dt:
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12/08/1998
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Title:
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OPERATIONAL AMPLIFIER WITH CMOS TRANSISTORS MADE USING 2.5 VOLT PROCESS TRANSISTORS
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09208203
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Filing Dt:
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12/09/1998
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Title:
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EFFICIENT INTERCONNECT NETWORK FOR USE IN FPGA DEVICE HAVING VARIABLE GRAIN ARCHITECTURE
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09212022
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Filing Dt:
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12/15/1998
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Title:
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METHODS FOR CONFIGURING FPGA'S HAVING VARIABLE GRAIN COMPONENTS FOR PROVIDING TIME-SHARED ACCESS TO INTERCONNECT RESOURCES
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09212330
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Filing Dt:
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12/15/1998
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Title:
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METHODS FOR CONFIGURING FPGA'S HAVING VARIABLE GRAIN BLOCKS AND LOGIC FOR PROVIDING TIME-SHARED ACCESS TO INTERCONNECT RESOURCES
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09216051
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Filing Dt:
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12/18/1998
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Title:
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METHOD OF FORMING A NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
|
03/20/2001
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Application #:
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09216662
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Filing Dt:
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12/16/1998
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Title:
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METHODS FOR CONFIGURING FPGA'S HAVING VARIABLE GRAIN BLOCKS AND SHARED LOGIC FOR PROVIDING SYMMETRIC ROUTING OF RESULT OUTPUT TO DIFFERENTLY-DIRECTED AND TRISTATEABLE INTERCONNECT RESOURCES
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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09217647
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Filing Dt:
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12/21/1998
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Title:
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EEPROM CELL USING P-WELL FOR TUNNELING ACROSS A CHANNEL
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09217648
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Filing Dt:
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12/21/1998
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Title:
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FLOATING GATE MEMORY CELL STRUCTURE WITH PROGRAMMING MECHANISM OUTSIDE THE READ PATH
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Patent #:
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Issue Dt:
|
09/25/2001
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Application #:
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09218987
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Filing Dt:
|
12/22/1998
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Title:
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EEPROM CELL WITH TUNNELING AT SEPARATE EDGE AND CHANNEL REGIONS
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Patent #:
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|
Issue Dt:
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05/16/2000
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Application #:
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09220201
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Filing Dt:
|
12/23/1998
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Title:
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FLOATING GATE MEMORY APPARATUS AND METHOD FOR SELECTED PROGRAMMING THEREOF
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09220469
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Filing Dt:
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12/23/1998
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Title:
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AVALANCHE PROGRAMMED FLOATING GATE MEMORY CELL STRUCTURE WITH PROGRAM ELEMENT IN FIRST POLYSILICON LAYER
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09221360
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Filing Dt:
|
12/28/1998
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Title:
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AVALANCHE PROGRAMMED FLOATING GATE MEMORY CELL STRUCTURE WITH PROGRAM ELEMENT IN POLYSILICON
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Patent #:
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Issue Dt:
|
04/10/2001
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Application #:
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09226702
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Filing Dt:
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01/07/1999
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Title:
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PMOS AVALANCHE PROGRAMMED FLOATING GATE MEMORY CELL STRUCTURE
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Patent #:
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Issue Dt:
|
03/06/2001
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Application #:
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09227981
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Filing Dt:
|
01/08/1999
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Title:
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OXIDE FORMATION PROCESS FOR MANUFACTURING PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
|
01/30/2001
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Application #:
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09235351
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Filing Dt:
|
01/21/1999
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Title:
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FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS AND INTERCONNECT CHANNEL FOR BROADCASTING ADDRESS AND CONTROL SIGNALS
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Patent #:
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|
Issue Dt:
|
08/01/2000
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Application #:
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09235356
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Filing Dt:
|
01/21/1999
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Title:
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MULTI-PORT SRAM CELL ARRAY HAVING PLURAL WRITE PATHS INCLUDING FOR WRITING THROUGH ADDRESSABLE PORT AND THROUGH SERIAL BOUNDARY SCAN
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Patent #:
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|
Issue Dt:
|
04/03/2001
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Application #:
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09235615
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Filing Dt:
|
01/21/1999
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Title:
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FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS WITH REGISTERED ADDRESS AND DATA INPUT SECTIONS
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Patent #:
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|
Issue Dt:
|
12/07/1999
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Application #:
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09239072
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Filing Dt:
|
01/27/1999
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|
Title:
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TWO TRANSISTOR EEPROM CELL USING P-WELL FOR TUNNELING ACROSS A CHANNEL
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|
|
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Patent #:
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|
Issue Dt:
|
10/02/2001
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Application #:
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09240560
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Filing Dt:
|
01/29/1999
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Title:
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PROCESS FOR MANUFACTURING SHALLOW TRENCHES FILLED WITH DIELECTRIC MATERIAL HAVING LOW MECHANICAL STRESS
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Patent #:
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|
Issue Dt:
|
09/25/2001
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Application #:
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09245813
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Filing Dt:
|
02/05/1999
|
|
Title:
|
TWO TRANSISTOR EEPROM CELL
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Patent #:
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|
Issue Dt:
|
07/03/2001
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Application #:
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09255053
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Filing Dt:
|
02/22/1999
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|
Title:
|
PROCESS FOR FABRICATING A HIGH-ENDURANCE NON-VOLATILE MEMORY DEVICE
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Patent #:
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|
Issue Dt:
|
06/13/2000
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Application #:
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09255410
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Filing Dt:
|
02/22/1999
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|
Title:
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METHOD FOR SORTING SEMICONDUCTOR DEVICES HAVING A PLURALITY OF NON-VOLATILE MEMORY CELLS
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Patent #:
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|
Issue Dt:
|
10/17/2000
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Application #:
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09256245
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Filing Dt:
|
02/23/1999
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Title:
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FABRICATION OF OXIDE REGIONS HAVING MULTIPLE THICKNESSES USING MINIMIZED NUMBER OF THERMAL CYCLES
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Patent #:
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|
Issue Dt:
|
06/13/2000
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Application #:
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09263412
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Filing Dt:
|
03/05/1999
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Title:
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SEMICONDUCTOR DEVICE HAVING A MULTI-LAYER METAL INTERCONNECT STRUCTURE
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Patent #:
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|
Issue Dt:
|
03/27/2001
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Application #:
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09268897
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Filing Dt:
|
03/16/1999
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Title:
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NON-VOLATILE MEMORY DEVICE HAVING A HIGH-RELIABILITY COMPOSITE INSULATON LAYER
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09276068
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Filing Dt:
|
03/25/1999
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Publication #:
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Pub Dt:
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02/14/2002
| | | | |
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Title:
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FARICATION OF HIGH QUALITY OXIDES BY CONTROLLING SPACING BETWEEN SEMICONDUCTOR WAFERS DURING PROCESSING
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Patent #:
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|
Issue Dt:
|
12/19/2000
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Application #:
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09276990
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Filing Dt:
|
03/26/1999
|
|
Title:
|
HIGH VOLTAGE DETECTOR TO CONTROL A POWER SUPPLY VOLTAGE PUMP FOR A 2.5 VOLT SEMICONDUCTOR PROCESS DEVICE
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|
|
|
Patent #:
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|
Issue Dt:
|
02/29/2000
|
Application #:
|
09276991
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Filing Dt:
|
03/26/1999
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|
Title:
|
BAND GAP REFERENCE USING A LOW VOLTAGE POWER SUPPLY
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|
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Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09277441
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Filing Dt:
|
03/26/1999
|
|
Title:
|
AVALANCHE INJECTION EEPROM MEMORY CELL WITH P-TYPE CONTROL GATE
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|
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Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09280887
|
Filing Dt:
|
03/29/1999
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|
Title:
|
BORON DOPED SILICON CAPACITOR PLATE
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Patent #:
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|
Issue Dt:
|
09/04/2001
|
Application #:
|
09286830
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Filing Dt:
|
04/06/1999
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Title:
|
ANGLED NITROGEN ION IMPLANTATION FOR MINIMIZING MECHANICAL STRESS ON SIDE WALLS OF AN ISOLATION TRENCH
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Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09287976
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Filing Dt:
|
04/07/1999
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|
Publication #:
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Pub Dt:
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01/24/2002
| | | | |
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Title:
|
HIGH DIELECTRIC GATE INSULATOR PROCESS FOR NANOMETER MOSFETS
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Patent #:
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|
Issue Dt:
|
07/23/2002
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Application #:
|
09310071
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Filing Dt:
|
05/11/1999
|
|
Title:
|
FLOATING GATE MEMORY APPARATUS AND METHOD FOR SELECTED PROGRAMMING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09316241
|
Filing Dt:
|
05/21/1999
|
|
Title:
|
TRIPLE-WELL EEPROM CELL USING P-WELL FOR TUNNELING ACROSS A CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
09334051
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Filing Dt:
|
06/15/1999
|
|
Title:
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ZERO-POWER CMOS NON VOLATILE MEMORY CELL HAVING AN AVALANCHE INJECTION ELEMENT
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Patent #:
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|
Issue Dt:
|
03/07/2000
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Application #:
|
09334052
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Filing Dt:
|
06/15/1999
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|
Title:
|
NON-VOLATILE MEMORY CELL HAVING DUAL AVALANCHE INJECTION ELEMENTS
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Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09454322
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Filing Dt:
|
12/03/1999
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|
Title:
|
INVERSION OF PRODUCT TERM LINE BEFORE OR LOGIC IN A PROGRAMMABLE LOGIC DEVICE (PLD)
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Patent #:
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|
Issue Dt:
|
11/21/2000
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Application #:
|
09472645
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Filing Dt:
|
12/27/1999
|
|
Title:
|
VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS
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|
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Patent #:
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|
Issue Dt:
|
02/26/2002
|
Application #:
|
09548171
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Filing Dt:
|
04/13/2000
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Title:
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Output buffer for making a high voltage (5.0 volt) compatible input/output in a low voltage (2.5volt)semiconductor process
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Patent #:
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|
Issue Dt:
|
09/18/2001
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Application #:
|
09603119
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Filing Dt:
|
06/22/2000
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|
Title:
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Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources
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Patent #:
|
|
Issue Dt:
|
04/10/2001
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Application #:
|
09603807
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Filing Dt:
|
06/26/2000
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|
Title:
|
AN FPGA DEVICE AND METHOD THAT INCLUDES A VARIABLE GRAIN FUNCTION ARCHITECTURE FOR IMPLEMENTING CONFIGURATION LOGIC BLOCKS AND A COMPLIMENTARY VARIABLE LENGTH INTERCONNECT ARCHITECTURE FOR PROVIDING CONFIGURABLE ROUTING BETWEEN CONFIGURATION LOGIC BLOCKS
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Patent #:
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|
Issue Dt:
|
04/30/2002
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Application #:
|
09626094
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Filing Dt:
|
07/26/2000
|
|
Title:
|
VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS
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|
|
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Patent #:
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|
Issue Dt:
|
09/24/2002
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Application #:
|
09651805
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Filing Dt:
|
11/09/2000
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Title:
|
PROCESS FOR MANUFACTURING SHALLOW TRENCHES FILLED WITH DIELECTRIC MATERIAL HAVING LOW MECHANICAL STRESS
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|
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|
Patent #:
|
|
Issue Dt:
|
06/19/2001
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Application #:
|
09669186
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Filing Dt:
|
09/25/2000
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Title:
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Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources
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Patent #:
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|
Issue Dt:
|
02/25/2003
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Application #:
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09733878
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Filing Dt:
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12/08/2000
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Publication #:
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Pub Dt:
|
12/27/2001
| | | | |
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Title:
|
METHODS FOR CONFIGURING FPGA'S HAVING VARIABLE GRAIN BLOCKS AND SHARED LOGIC FOR PROVIDING SYMMETRIC ROUTING OF RESULT OUTPUT TO DIFFERENTLY-DIRECTED AND TRISTATEABLE INTERCONNECT RESOURCES
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
09745626
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Filing Dt:
|
12/20/2000
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|
Publication #:
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Pub Dt:
|
05/10/2001
| | | | |
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Title:
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Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09757407
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Filing Dt:
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01/08/2001
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Publication #:
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Pub Dt:
|
09/20/2001
| | | | |
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Title:
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Gate isolated triple-well non-volatile cell
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Patent #:
|
NONE
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Issue Dt:
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Application #:
|
09782409
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Filing Dt:
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02/12/2001
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Publication #:
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Pub Dt:
|
08/23/2001
| | | | |
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Title:
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SEMICONDUCTOR-OXIDE-SEMICONDUCTOR CAPACITOR FORMED IN
INTEGRATED CIRCUIT
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|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
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Application #:
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09841209
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Filing Dt:
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04/23/2001
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Publication #:
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Pub Dt:
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12/26/2002
| | | | |
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Title:
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METHODS FOR CONFIGURING FPGA ' S HAVING VARIABLE GRAIN COMPONENTS FOR PROVIDING TIME-SHARED ACCESS TO INTERCONNECT RESOURCES
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