|
Total properties:
99
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/1975
|
Application #:
|
05307863
|
Filing Dt:
|
11/20/1972
|
|
Title:
|
A LSI PROGRAMMABLE PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/1975
|
Application #:
|
05307863
|
Filing Dt:
|
11/20/1972
|
|
Title:
|
A LSI PROGRAMMABLE PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/1975
|
Application #:
|
05391963
|
Filing Dt:
|
|
|
Title:
|
OVERLAP TIMING CONTROL CIRCUIT FOR CONDITIONING SIGNALS IN A SEMICONDU CTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/1975
|
Application #:
|
05391963
|
Filing Dt:
|
|
|
Title:
|
OVERLAP TIMING CONTROL CIRCUIT FOR CONDITIONING SIGNALS IN A SEMICONDU CTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/1975
|
Application #:
|
05402503
|
Filing Dt:
|
10/01/1973
|
|
Title:
|
CONCURRENT DATA ADDRESS AND REFRESH CONTROL FOR A VOLATILE LSI MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/1975
|
Application #:
|
05402503
|
Filing Dt:
|
10/01/1973
|
|
Title:
|
CONCURRENT DATA ADDRESS AND REFRESH CONTROL FOR A VOLATILE LSI MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1976
|
Application #:
|
05527358
|
Filing Dt:
|
11/26/1974
|
|
Title:
|
MULTI-MICROPROCESSOR UNIT ON A SINGLE SEMICONDUCTOR CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1976
|
Application #:
|
05527358
|
Filing Dt:
|
11/26/1974
|
|
Title:
|
MULTI-MICROPROCESSOR UNIT ON A SINGLE SEMICONDUCTOR CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1976
|
Application #:
|
05537680
|
Filing Dt:
|
12/30/1974
|
|
Title:
|
FIFO BUFFER REGISTER MEMORY UTILIZING A ONESHOT DATA TRANSFER SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1976
|
Application #:
|
05537680
|
Filing Dt:
|
12/30/1974
|
|
Title:
|
FIFO BUFFER REGISTER MEMORY UTILIZING A ONESHOT DATA TRANSFER SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/1977
|
Application #:
|
05578094
|
Filing Dt:
|
05/16/1975
|
|
Title:
|
CAPACITTOR MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/1977
|
Application #:
|
05578094
|
Filing Dt:
|
05/16/1975
|
|
Title:
|
CAPACITTOR MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/1977
|
Application #:
|
05594579
|
Filing Dt:
|
|
|
Title:
|
ULTRA HIGH SENSITIVITY SENSE AMPLIFIER FOR MEMORIES EMPLOYING SINGLE T RANSISTOR CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/1977
|
Application #:
|
05594579
|
Filing Dt:
|
|
|
Title:
|
ULTRA HIGH SENSITIVITY SENSE AMPLIFIER FOR MEMORIES EMPLOYING SINGLE T RANSISTOR CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/1977
|
Application #:
|
05594669
|
Filing Dt:
|
|
|
Title:
|
INTERLACED MEMORY MATRIX ARRAY HAVING SINGLE TRANSISTOR CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/1977
|
Application #:
|
05594669
|
Filing Dt:
|
|
|
Title:
|
INTERLACED MEMORY MATRIX ARRAY HAVING SINGLE TRANSISTOR CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
|
Application #:
|
05604705
|
Filing Dt:
|
|
|
Title:
|
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
|
Application #:
|
05604705
|
Filing Dt:
|
|
|
Title:
|
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1976
|
Application #:
|
05630218
|
Filing Dt:
|
11/10/1975
|
|
Title:
|
MOS INTEGRATED CIRCUIT CHIP FOR DISPLAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1976
|
Application #:
|
05630218
|
Filing Dt:
|
11/10/1975
|
|
Title:
|
MOS INTEGRATED CIRCUIT CHIP FOR DISPLAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/1977
|
Application #:
|
05637177
|
Filing Dt:
|
|
|
Title:
|
METHOD FOR MAKING TRANSISTOR STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/1977
|
Application #:
|
05637177
|
Filing Dt:
|
|
|
Title:
|
METHOD FOR MAKING TRANSISTOR STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/1977
|
Application #:
|
05658705
|
Filing Dt:
|
02/17/1976
|
|
Title:
|
HIGH SPEED DIFFERENTIAL TO TTL CONVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/1977
|
Application #:
|
05658705
|
Filing Dt:
|
02/17/1976
|
|
Title:
|
HIGH SPEED DIFFERENTIAL TO TTL CONVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/1977
|
Application #:
|
05674391
|
Filing Dt:
|
04/07/1976
|
|
Title:
|
DYNAMIC MEMORY REFRESH METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/1977
|
Application #:
|
05674391
|
Filing Dt:
|
04/07/1976
|
|
Title:
|
DYNAMIC MEMORY REFRESH METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/1978
|
Application #:
|
05792578
|
Filing Dt:
|
05/02/1977
|
|
Title:
|
IGFET INTEGRATED CIRCUIT MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/1978
|
Application #:
|
05792578
|
Filing Dt:
|
05/02/1977
|
|
Title:
|
IGFET INTEGRATED CIRCUIT MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
|
Application #:
|
05813001
|
Filing Dt:
|
|
|
Title:
|
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
|
Application #:
|
05813001
|
Filing Dt:
|
|
|
Title:
|
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/1979
|
Application #:
|
05834928
|
Filing Dt:
|
09/20/1977
|
|
Title:
|
ORGANIZATION FOR AN INTEGRATED CIRCUIT CALCULATOR/CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/1979
|
Application #:
|
05834928
|
Filing Dt:
|
09/20/1977
|
|
Title:
|
ORGANIZATION FOR AN INTEGRATED CIRCUIT CALCULATOR/CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
|
Application #:
|
05839342
|
Filing Dt:
|
|
|
Title:
|
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
|
Application #:
|
05839342
|
Filing Dt:
|
|
|
Title:
|
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/1978
|
Application #:
|
05864247
|
Filing Dt:
|
12/27/1977
|
|
Title:
|
METHOD OF MAKING A V-MOSFIELD EFFECT TRANSISTOR FOR DYNAMIC MEMORY CE LL HAVING IMPROVED CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/1978
|
Application #:
|
05864247
|
Filing Dt:
|
12/27/1977
|
|
Title:
|
METHOD OF MAKING A V-MOSFIELD EFFECT TRANSISTOR FOR DYNAMIC MEMORY CE LL HAVING IMPROVED CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/1980
|
Application #:
|
05875783
|
Filing Dt:
|
02/07/1978
|
|
Title:
|
COMPENSATED MOS TIMING NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/1980
|
Application #:
|
05875783
|
Filing Dt:
|
02/07/1978
|
|
Title:
|
COMPENSATED MOS TIMING NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/1979
|
Application #:
|
05907725
|
Filing Dt:
|
05/19/1978
|
|
Title:
|
IGFET INTEGRATED CIRCUIT MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/1979
|
Application #:
|
05907725
|
Filing Dt:
|
05/19/1978
|
|
Title:
|
IGFET INTEGRATED CIRCUIT MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/1981
|
Application #:
|
05958255
|
Filing Dt:
|
11/06/1978
|
|
Title:
|
HIGH SPEED, LOW COMPONENT COUNT, CML EXCLUSIVE NOR GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/1981
|
Application #:
|
05958255
|
Filing Dt:
|
11/06/1978
|
|
Title:
|
HIGH SPEED, LOW COMPONENT COUNT, CML EXCLUSIVE NOR GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/1979
|
Application #:
|
05966326
|
Filing Dt:
|
12/04/1978
|
|
Title:
|
METHOD OF FORMING A METAL INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/1979
|
Application #:
|
05966326
|
Filing Dt:
|
12/04/1978
|
|
Title:
|
METHOD OF FORMING A METAL INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/1983
|
Application #:
|
05970580
|
Filing Dt:
|
12/18/1978
|
|
Title:
|
OXIDATION OF SILICON WAFERS TO ELIMINATE WHITE RIBBON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/1983
|
Application #:
|
05970580
|
Filing Dt:
|
12/18/1978
|
|
Title:
|
OXIDATION OF SILICON WAFERS TO ELIMINATE WHITE RIBBON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/1980
|
Application #:
|
05973175
|
Filing Dt:
|
12/26/1978
|
|
Title:
|
DECODER FOR A PROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/1980
|
Application #:
|
05973175
|
Filing Dt:
|
12/26/1978
|
|
Title:
|
DECODER FOR A PROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/1980
|
Application #:
|
05973928
|
Filing Dt:
|
12/28/1978
|
|
Title:
|
TECHNIQUE OF GROWING THIN SILICON OXIDE FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/1980
|
Application #:
|
05973928
|
Filing Dt:
|
12/28/1978
|
|
Title:
|
TECHNIQUE OF GROWING THIN SILICON OXIDE FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/1981
|
Application #:
|
06017842
|
Filing Dt:
|
03/06/1979
|
|
Title:
|
SINGLE MASK METHOD OF FABRICATING COMPLEMENTARY INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/1981
|
Application #:
|
06017842
|
Filing Dt:
|
03/06/1979
|
|
Title:
|
SINGLE MASK METHOD OF FABRICATING COMPLEMENTARY INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1981
|
Application #:
|
06053084
|
Filing Dt:
|
06/28/1979
|
|
Title:
|
CHARGE RESTORE CIRCUIT FOR SEMICONDUCTOR MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1981
|
Application #:
|
06053084
|
Filing Dt:
|
06/28/1979
|
|
Title:
|
CHARGE RESTORE CIRCUIT FOR SEMICONDUCTOR MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1981
|
Application #:
|
06072446
|
Filing Dt:
|
09/04/1979
|
|
Title:
|
RAM HAVING A STABILIZED SUBSTRATE BIAS AND LOW-THRESHOLD NARROW-WIDTH TRANSFER GATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1981
|
Application #:
|
06072446
|
Filing Dt:
|
09/04/1979
|
|
Title:
|
RAM HAVING A STABILIZED SUBSTRATE BIAS AND LOW-THRESHOLD NARROW-WIDTH TRANSFER GATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1981
|
Application #:
|
06080618
|
Filing Dt:
|
10/01/1979
|
|
Title:
|
FABRICATION OF INTEGRATED CIRCUITS EMPLOYING ONLY ION IMPLANTATION FOR ALL DOPANT LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1981
|
Application #:
|
06080618
|
Filing Dt:
|
10/01/1979
|
|
Title:
|
FABRICATION OF INTEGRATED CIRCUITS EMPLOYING ONLY ION IMPLANTATION FOR ALL DOPANT LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1982
|
Application #:
|
06099515
|
Filing Dt:
|
12/03/1979
|
|
Title:
|
METHOD FOR MASS PRODUCING MINIATURE FIELD EFFECT TRANSISTORS IN HIGH DENSITY LSI/VLSI CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1982
|
Application #:
|
06099515
|
Filing Dt:
|
12/03/1979
|
|
Title:
|
METHOD FOR MASS PRODUCING MINIATURE FIELD EFFECT TRANSISTORS IN HIGH DENSITY LSI/VLSI CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1982
|
Application #:
|
06113388
|
Filing Dt:
|
01/18/1980
|
|
Title:
|
METHOD OF FABRICATING A CHARGE TRANSFER CHANNEL COVERED BY A STEPPED INSULATING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1982
|
Application #:
|
06113388
|
Filing Dt:
|
01/18/1980
|
|
Title:
|
METHOD OF FABRICATING A CHARGE TRANSFER CHANNEL COVERED BY A STEPPED INSULATING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1982
|
Application #:
|
06118496
|
Filing Dt:
|
02/04/1980
|
|
Title:
|
HERMETIC INTEGRATED CIRCUIT PACKAGE FOR HIGH DENSITY HIGH POWER APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1982
|
Application #:
|
06118496
|
Filing Dt:
|
02/04/1980
|
|
Title:
|
HERMETIC INTEGRATED CIRCUIT PACKAGE FOR HIGH DENSITY HIGH POWER APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/1983
|
Application #:
|
06153090
|
Filing Dt:
|
05/27/1980
|
|
Title:
|
METHOD OF FABRICATING A MISALIGNED, COMPOSITE ELECTRICAL CONTACT ON A SEMICONDUCTOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/1983
|
Application #:
|
06153090
|
Filing Dt:
|
05/27/1980
|
|
Title:
|
METHOD OF FABRICATING A MISALIGNED, COMPOSITE ELECTRICAL CONTACT ON A SEMICONDUCTOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/1981
|
Application #:
|
06155533
|
Filing Dt:
|
06/02/1980
|
|
Title:
|
ELECTRONIC PACKAGE FOR HIGH DENSITY INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/1981
|
Application #:
|
06155533
|
Filing Dt:
|
06/02/1980
|
|
Title:
|
ELECTRONIC PACKAGE FOR HIGH DENSITY INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1982
|
Application #:
|
06164211
|
Filing Dt:
|
06/30/1980
|
|
Title:
|
ECC CHECK BIT GENERATION USING THROUGH CHECKING PARITY BITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1982
|
Application #:
|
06164211
|
Filing Dt:
|
06/30/1980
|
|
Title:
|
ECC CHECK BIT GENERATION USING THROUGH CHECKING PARITY BITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/1983
|
Application #:
|
06179311
|
Filing Dt:
|
08/18/1980
|
|
Title:
|
SUPERCONDUCTIVE TUNNEL JUNCTION DEVICE AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/1983
|
Application #:
|
06179311
|
Filing Dt:
|
08/18/1980
|
|
Title:
|
SUPERCONDUCTIVE TUNNEL JUNCTION DEVICE AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/1983
|
Application #:
|
06200997
|
Filing Dt:
|
10/27/1980
|
|
Title:
|
JFET DYNAMIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/1983
|
Application #:
|
06200997
|
Filing Dt:
|
10/27/1980
|
|
Title:
|
JFET DYNAMIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/1984
|
Application #:
|
06277629
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Filing Dt:
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06/26/1981
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Title:
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FIELD EFFECT CURRENT MODE LOGIC GATE
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Patent #:
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Issue Dt:
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06/05/1984
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Application #:
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06282919
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Filing Dt:
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07/13/1981
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Title:
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EXTENDED ADDRESS GENERATING APPARATUS AND METHOD
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Patent #:
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Issue Dt:
|
06/05/1984
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Application #:
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06282919
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Filing Dt:
|
07/13/1981
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|
Title:
|
EXTENDED ADDRESS GENERATING APPARATUS AND METHOD
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Patent #:
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Issue Dt:
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10/18/1983
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Application #:
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06305320
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Filing Dt:
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09/24/1981
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Title:
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GALLIUM ARSENIDE TO EMITTER COUPLED LOGIC LEVEL CONVERTER
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Patent #:
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Issue Dt:
|
10/18/1983
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Application #:
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06305320
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Filing Dt:
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09/24/1981
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Title:
|
GALLIUM ARSENIDE TO EMITTER COUPLED LOGIC LEVEL CONVERTER
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Patent #:
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Issue Dt:
|
01/24/1984
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Application #:
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06338204
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Filing Dt:
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01/11/1982
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Title:
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SELECTIVE EPITAXIAL ETCH PLANAR PROCESSING FOR GALLIUM ARSENIDE SEMICONDUCTORS
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Patent #:
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Issue Dt:
|
01/24/1984
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Application #:
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06338204
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Filing Dt:
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01/11/1982
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Title:
|
SELECTIVE EPITAXIAL ETCH PLANAR PROCESSING FOR GALLIUM ARSENIDE SEMICONDUCTORS
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Patent #:
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Issue Dt:
|
04/03/1984
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Application #:
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06339022
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Filing Dt:
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01/13/1982
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Title:
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STORAGE LOGIC/ARRAY (SLA) CIRCUIT
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Patent #:
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Issue Dt:
|
04/03/1984
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Application #:
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06339022
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Filing Dt:
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01/13/1982
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Title:
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STORAGE LOGIC/ARRAY (SLA) CIRCUIT
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Patent #:
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Issue Dt:
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10/16/1984
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Application #:
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06355804
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Filing Dt:
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03/08/1982
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Title:
|
PARITY GENERATION/DETECTION LOGIC CIRCUIT FROM TRANSFER GATES
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Patent #:
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Issue Dt:
|
10/16/1984
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Application #:
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06355804
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Filing Dt:
|
03/08/1982
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|
Title:
|
PARITY GENERATION/DETECTION LOGIC CIRCUIT FROM TRANSFER GATES
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|
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Patent #:
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Issue Dt:
|
12/11/1984
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Application #:
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06444267
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Filing Dt:
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11/24/1982
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Title:
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SEMICONDUCTOR DIE-ATTACH TECHNIQUE AND COMPOSITION THEREFOR
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|
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Patent #:
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Issue Dt:
|
12/11/1984
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Application #:
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06444267
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Filing Dt:
|
11/24/1982
|
|
Title:
|
SEMICONDUCTOR DIE-ATTACH TECHNIQUE AND COMPOSITION THEREFOR
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|
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Patent #:
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Issue Dt:
|
04/02/1985
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Application #:
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06457175
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Filing Dt:
|
01/11/1983
|
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Title:
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RE-PROGRAMMABLE PLA
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|
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Patent #:
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Issue Dt:
|
04/02/1985
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Application #:
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06457175
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Filing Dt:
|
01/11/1983
|
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Title:
|
RE-PROGRAMMABLE PLA
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Patent #:
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Issue Dt:
|
07/30/1985
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Application #:
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06513393
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Filing Dt:
|
07/14/1983
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|
Title:
|
CONTENT ADDRESSABLE MEMORY CELL
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|
|
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Patent #:
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|
Issue Dt:
|
07/30/1985
|
Application #:
|
06513393
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Filing Dt:
|
07/14/1983
|
|
Title:
|
CONTENT ADDRESSABLE MEMORY CELL
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/01/1986
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Application #:
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06518166
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Filing Dt:
|
07/28/1983
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|
Title:
|
COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DUAL PORT RANDOM ACCESS MEMORY CELL
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|
|
|
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Patent #:
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Issue Dt:
|
04/01/1986
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Application #:
|
06518166
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Filing Dt:
|
07/28/1983
|
|
Title:
|
COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DUAL PORT RANDOM ACCESS MEMORY CELL
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Patent #:
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Issue Dt:
|
07/23/1985
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Application #:
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06580291
|
Filing Dt:
|
02/21/1984
|
|
Title:
|
ALLUMINUM - REFRACTORY METAL INTERCONNECT W/ANODIZED PERIPHERY
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|
|
|
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Patent #:
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|
Issue Dt:
|
07/23/1985
|
Application #:
|
06580291
|
Filing Dt:
|
02/21/1984
|
|
Title:
|
ALLUMINUM - REFRACTORY METAL INTERCONNECT W/ANODIZED PERIPHERY
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/30/1986
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Application #:
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06699028
|
Filing Dt:
|
02/07/1985
|
|
Title:
|
SEMI-CONDUCTOR DEVICE WITH SANDWICH PASSIVATION COATING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/30/1986
|
Application #:
|
06699028
|
Filing Dt:
|
02/07/1985
|
|
Title:
|
SEMI-CONDUCTOR DEVICE WITH SANDWICH PASSIVATION COATING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/17/1987
|
Application #:
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06819995
|
Filing Dt:
|
01/21/1986
|
|
Title:
|
EPOXY-GLASS INTEGRATED CIRCUIT PACKAGE HAVING BONDING PADS IN A STEPPED CAVITY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/1987
|
Application #:
|
06819995
|
Filing Dt:
|
01/21/1986
|
|
Title:
|
EPOXY-GLASS INTEGRATED CIRCUIT PACKAGE HAVING BONDING PADS IN A STEPPED CAVITY
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|
