|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
13035617
|
Filing Dt:
|
02/25/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A WAFER LEVEL PACKAGE STRUCTURE USING CONDUCTIVE VIA AND EXPOSED BUMP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
13035669
|
Filing Dt:
|
02/25/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER AND OPPOSING BUILD-UP INTERCONNECT STRUCTURE WITH CONNECTING CONDUCTIVE TMV FOR ELECTRICAL INTERCONNECT OF FO-WLCSP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13037181
|
Filing Dt:
|
02/28/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BUMP STRUCTURE WITH INSULATING BUFFER LAYER TO REDUCE STRESS ON SEMICONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13038384
|
Filing Dt:
|
03/01/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13038843
|
Filing Dt:
|
03/02/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13039309
|
Filing Dt:
|
03/02/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP BONDED DIES AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
13039311
|
Filing Dt:
|
03/03/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
13041869
|
Filing Dt:
|
03/07/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT AND METHOD FOR MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13042457
|
Filing Dt:
|
03/07/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM USING B-STAGE POLYMER AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
13043179
|
Filing Dt:
|
03/08/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER SEMICONDUCTOR DIE MOUNTED TO TSV INTERPOSER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13045523
|
Filing Dt:
|
03/10/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH UNDERFILLING STRUCTURES AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2015
|
Application #:
|
13048771
|
Filing Dt:
|
03/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
|
Title:
|
Semiconductor Device Having Embedded Integrated Passive Devices Electrically Interconnected Using Conductive Pillars
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13048859
|
Filing Dt:
|
03/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME STACKING MODULE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13052588
|
Filing Dt:
|
03/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A THERMALLY REINFORCED SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13052590
|
Filing Dt:
|
03/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STEP MOLD AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2015
|
Application #:
|
13052816
|
Filing Dt:
|
03/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A FLIP CHIP AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2013
|
Application #:
|
13053096
|
Filing Dt:
|
03/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
13053141
|
Filing Dt:
|
03/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
|
Title:
|
SEMICONDUCTOR PACKAGE SYSTEM WITH FINE PITCH LEAD FINGERS AND METHOD OF MANUFACTURING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13053142
|
Filing Dt:
|
03/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
13053719
|
Filing Dt:
|
03/22/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2016
|
Application #:
|
13069191
|
Filing Dt:
|
03/22/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Leadframe With Notched Fingers for Stacking Semiconductor Die
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13069744
|
Filing Dt:
|
03/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED LEADS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13069980
|
Filing Dt:
|
03/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2012
|
Application #:
|
13070219
|
Filing Dt:
|
03/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CONDUCTIVE STRUCTURE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13070291
|
Filing Dt:
|
03/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIPCHIP LEADFRAME AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13070362
|
Filing Dt:
|
03/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEVELING STANDOFF AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
13070789
|
Filing Dt:
|
03/24/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
13070899
|
Filing Dt:
|
03/24/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME ETCHING AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13071228
|
Filing Dt:
|
03/24/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER SHIELD AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13071397
|
Filing Dt:
|
03/24/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COLLAPSED MULTI-INTEGRATION PACKAGE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13071433
|
Filing Dt:
|
03/24/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LOCKING INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13071449
|
Filing Dt:
|
03/24/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13071514
|
Filing Dt:
|
03/25/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
13071760
|
Filing Dt:
|
03/25/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSPARENT ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
13072603
|
Filing Dt:
|
03/25/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM FOR ELECTROMAGNETIC INTERFERENCE SHIELDING AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
13080070
|
Filing Dt:
|
04/05/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
13080469
|
Filing Dt:
|
04/05/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2011
| | | | |
|
Title:
|
ETCHED RECESS PACKAGE ON PACKAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13081011
|
Filing Dt:
|
04/06/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT AND METHOD FOR MANUFACTURING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2012
|
Application #:
|
13081227
|
Filing Dt:
|
04/06/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
|
Title:
|
METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13085475
|
Filing Dt:
|
04/12/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2012
|
Application #:
|
13088647
|
Filing Dt:
|
04/18/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/08/2011
| | | | |
|
Title:
|
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
13090192
|
Filing Dt:
|
04/19/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOUNTABLE INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
13090590
|
Filing Dt:
|
04/20/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING IPD STRUCTURE WITH SMOOTH CONDUCTIVE LAYER AND BOTTOM-SIDE CONDUCTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2012
|
Application #:
|
13095680
|
Filing Dt:
|
04/27/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13098419
|
Filing Dt:
|
04/30/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar Frame
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
|
13098426
|
Filing Dt:
|
04/30/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER ACTIVE SURFACE OF SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13098438
|
Filing Dt:
|
04/30/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13098440
|
Filing Dt:
|
04/30/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING TSV SEMICONDUCTOR DIE WITHIN ENCAPSULANT WITH TMV FOR VERTICAL INTERCONNECT IN POP
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13098443
|
Filing Dt:
|
04/30/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13098448
|
Filing Dt:
|
04/30/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming an Interconnect Structure with Conductive Material Recessed Within Conductive Ring Over Surface of Conductive Pillar
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13100235
|
Filing Dt:
|
05/03/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING COVER TO SEMICONDUCTOR DIE AND INTERPOSER WITH ADHESIVE MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13101657
|
Filing Dt:
|
05/05/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
|
Title:
|
WIREBONDLESS WAFER LEVEL PACKAGE WITH PLATED BUMPS AND INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13102041
|
Filing Dt:
|
05/05/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13102044
|
Filing Dt:
|
05/05/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTED CIRCUIT LEAD ARRAY AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13102047
|
Filing Dt:
|
05/05/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ELECTRICAL INTERFACE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13102052
|
Filing Dt:
|
05/05/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13105814
|
Filing Dt:
|
05/11/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2016
|
Application #:
|
13106591
|
Filing Dt:
|
05/12/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING LEADFRAME WITH CONDUCTIVE BODIES FOR VERTICAL ELECTRICAL INTERCONNECT OF SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2018
|
Application #:
|
13107075
|
Filing Dt:
|
05/13/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Dummy Pillars Between Semiconductor Die and Substrate for Maintaining Standoff Distance
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
13112172
|
Filing Dt:
|
05/20/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming 3D Semiconductor Package with Semiconductor Die Stacked Over Semiconductor Wafer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13112717
|
Filing Dt:
|
05/20/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/08/2011
| | | | |
|
Title:
|
THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13116328
|
Filing Dt:
|
05/26/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING EWLB PACKAGE CONTAINING STACKED SEMICONDUCTOR DIE ELECTRICALLY CONNECTED THROUGH CONDUCTIVE VIAS FORMED IN ENCAPSULANT AROUND DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
13117500
|
Filing Dt:
|
05/27/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13118214
|
Filing Dt:
|
05/27/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13118310
|
Filing Dt:
|
05/27/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13118955
|
Filing Dt:
|
05/31/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13149628
|
Filing Dt:
|
05/31/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming EWLB Semiconductor Package with Vertical Interconnect Structure and Cavity Region
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
13149669
|
Filing Dt:
|
05/31/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
13153286
|
Filing Dt:
|
06/03/2011
|
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF USING LEADFRAME BODIES TO FORM OPENINGS THROUGH ENCAPSULANT FOR VERTICAL INTERCONNECT OF SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13154308
|
Filing Dt:
|
06/06/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PROTRUDING PAD PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
13155312
|
Filing Dt:
|
06/07/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THREE-DIMENSIONAL VERTICALLY ORIENTED INTEGRATED CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13159095
|
Filing Dt:
|
06/13/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
|
Title:
|
METHOD FOR MANUFACTURE OF INLINE INTEGRATED CIRCUIT SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
13160799
|
Filing Dt:
|
06/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ISOLATION BARRIER AND METHOD FOR MANUFACTURING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13161008
|
Filing Dt:
|
06/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING WAFER SCALE HEAT SLUG SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
13161368
|
Filing Dt:
|
06/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13162513
|
Filing Dt:
|
06/16/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTRA SUBSTRATE DIE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
13162526
|
Filing Dt:
|
06/16/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE ON PACKAGE SUPPORT AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13162566
|
Filing Dt:
|
06/16/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT PACKAGING SYSTEM INCLUDING LASERING THROUGH ENCAPSULANT OVER INTERPOSER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
13163026
|
Filing Dt:
|
06/17/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming RF FEM and RF Transceiver in Semiconductor Package
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13163150
|
Filing Dt:
|
06/17/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LASER HOLE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13163523
|
Filing Dt:
|
06/17/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13163611
|
Filing Dt:
|
06/17/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL DISPERSAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13163643
|
Filing Dt:
|
06/17/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
METHOD OF MANUFACTURING INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13164015
|
Filing Dt:
|
06/20/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13164114
|
Filing Dt:
|
06/20/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13165658
|
Filing Dt:
|
06/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2012
|
Application #:
|
13166417
|
Filing Dt:
|
06/22/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE IN PACKAGE SYSTEM
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13166679
|
Filing Dt:
|
06/22/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13166802
|
Filing Dt:
|
06/22/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
13166809
|
Filing Dt:
|
06/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL EMISSION AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2015
|
Application #:
|
13167133
|
Filing Dt:
|
06/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming EWLB Package With Standoff Conductive Layer Over Encapsulant Bumps
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2015
|
Application #:
|
13167458
|
Filing Dt:
|
06/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A LEAD AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13167487
|
Filing Dt:
|
06/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE OVER SEED LAYER ON CONTACT PAD OF SEMICONDUCTOR DIE WITHOUT UNDERCUTTING SEED LAYER BENEATH INTERCONNECT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
13167566
|
Filing Dt:
|
06/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
13167631
|
Filing Dt:
|
06/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2016
|
Application #:
|
13167649
|
Filing Dt:
|
06/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WAFER LEVEL RECONFIGURATION AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2012
|
Application #:
|
13169387
|
Filing Dt:
|
06/27/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
|
Title:
|
PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/2015
|
Application #:
|
13170116
|
Filing Dt:
|
06/27/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
|
Title:
|
WAFER LEVEL DIE INTEGRATION AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13171341
|
Filing Dt:
|
06/28/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2012
|
Application #:
|
13172560
|
Filing Dt:
|
06/29/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING INTEGRATED CIRCUIT PACKAGE SYSTEM WITH UNDER PADDLE LEADFINGERS
|
|
