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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13314984
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Filing Dt:
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12/08/2011
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Publication #:
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Pub Dt:
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06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MAKING SINGLE LAYER SUBSTRATE WITH ASYMMETRICAL FIBERS AND REDUCED WARPAGE
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13314984
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Filing Dt:
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12/08/2011
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Publication #:
|
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Pub Dt:
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06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MAKING SINGLE LAYER SUBSTRATE WITH ASYMMETRICAL FIBERS AND REDUCED WARPAGE
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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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13315010
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Filing Dt:
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12/08/2011
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Publication #:
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Pub Dt:
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06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THICK ENCAPSULANT FOR STIFFNESS WITH RECESSES FOR STRESS RELIEF IN FO-WLCSP
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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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13315010
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Filing Dt:
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12/08/2011
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Publication #:
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Pub Dt:
|
06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THICK ENCAPSULANT FOR STIFFNESS WITH RECESSES FOR STRESS RELIEF IN FO-WLCSP
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Patent #:
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Issue Dt:
|
10/15/2013
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Application #:
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13315033
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Filing Dt:
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12/08/2011
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Publication #:
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Pub Dt:
|
06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING GUARD RING AROUND CONDUCTIVE TSV THROUGH SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
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13315033
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Filing Dt:
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12/08/2011
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|
Publication #:
|
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Pub Dt:
|
06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING GUARD RING AROUND CONDUCTIVE TSV THROUGH SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13324349
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Filing Dt:
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12/13/2011
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Publication #:
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Pub Dt:
|
06/13/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13324349
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Filing Dt:
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12/13/2011
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Publication #:
|
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Pub Dt:
|
06/13/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate
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Patent #:
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Issue Dt:
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10/15/2013
|
Application #:
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13324380
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Filing Dt:
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12/13/2011
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Publication #:
|
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Pub Dt:
|
04/12/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER INTERCONNECTIONS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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06/20/2017
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Application #:
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13324397
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Filing Dt:
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12/13/2011
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Publication #:
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Pub Dt:
|
06/13/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Recesses in Conductive Layer to Detect Continuity for Interconnect Between Semiconductor Die and Substrate
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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13324446
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Filing Dt:
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12/13/2011
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Publication #:
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Pub Dt:
|
06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM STRUCTURE ON BACK SURFACE OF TSV SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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13324446
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Filing Dt:
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12/13/2011
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Publication #:
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Pub Dt:
|
06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM STRUCTURE ON BACK SURFACE OF TSV SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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04/29/2014
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Application #:
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13325359
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Filing Dt:
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12/14/2011
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Publication #:
|
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Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SLUG AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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10/14/2014
|
Application #:
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13325395
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Filing Dt:
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12/14/2011
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Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE MOLD GATE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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13325530
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Filing Dt:
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12/14/2011
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Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT CONDUCTION AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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02/21/2017
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Application #:
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13325881
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Filing Dt:
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12/14/2011
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Publication #:
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|
Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE TRACE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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10/01/2013
|
Application #:
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13325903
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Filing Dt:
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12/14/2011
|
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Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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09/03/2013
|
Application #:
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13326090
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Filing Dt:
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12/14/2011
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Publication #:
|
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Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/29/2014
|
Application #:
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13326116
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Filing Dt:
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12/14/2011
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Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COUPLING FEATURES AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/26/2013
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Application #:
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13326128
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Filing Dt:
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12/14/2011
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Publication #:
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|
Pub Dt:
|
06/20/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE WITH CONDUCTIVE MICRO VIA ARRAY FOR 3-D FO-WLCSP
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Patent #:
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Issue Dt:
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11/26/2013
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Application #:
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13326128
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Filing Dt:
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12/14/2011
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Publication #:
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Pub Dt:
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06/20/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE WITH CONDUCTIVE MICRO VIA ARRAY FOR 3-D FO-WLCSP
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Patent #:
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Issue Dt:
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02/11/2014
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Application #:
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13326157
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Filing Dt:
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12/14/2011
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Publication #:
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Pub Dt:
|
07/26/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP WITH MULTIPLE ENCAPSULANTS
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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13326173
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Filing Dt:
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12/14/2011
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Publication #:
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Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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01/14/2014
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Application #:
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13326728
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Filing Dt:
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12/15/2011
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Publication #:
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Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACTS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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12/22/2015
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Application #:
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13326806
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Filing Dt:
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12/15/2011
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Publication #:
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Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINALS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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01/07/2014
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Application #:
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13326891
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Filing Dt:
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12/15/2011
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Publication #:
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Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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09/03/2013
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Application #:
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13327091
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Filing Dt:
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12/15/2011
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Publication #:
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Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSISTANCE MOLD AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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13327529
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Filing Dt:
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12/15/2011
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Publication #:
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Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/29/2017
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13327609
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Filing Dt:
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12/15/2011
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Publication #:
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Pub Dt:
|
06/20/2013
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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03/31/2015
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13327651
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Filing Dt:
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12/15/2011
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Publication #:
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Pub Dt:
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06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PERIMETER ANTIWARPAGE STRUCTURE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13333395
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Filing Dt:
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12/21/2011
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Publication #:
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Pub Dt:
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06/27/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13333395
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Filing Dt:
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12/21/2011
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Publication #:
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Pub Dt:
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06/27/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief
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Patent #:
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Issue Dt:
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06/04/2013
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Application #:
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13333739
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Filing Dt:
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12/21/2011
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Publication #:
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Pub Dt:
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05/09/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
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Patent #:
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Issue Dt:
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01/12/2016
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Application #:
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13334556
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Filing Dt:
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12/22/2011
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Publication #:
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Pub Dt:
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04/19/2012
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Title:
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Semiconductor Die and Method of Forming Noise Absorbing Regions Between THVs in Peripheral Region of the Die
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Patent #:
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Issue Dt:
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10/01/2013
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Application #:
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13335631
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Filing Dt:
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12/22/2011
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Publication #:
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Pub Dt:
|
04/19/2012
| | | | |
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Title:
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SEMICONDUCTOR PACKAGE HAVING SEMICONDUCTOR DIE WITH INTERNAL VERTICAL INTERCONNECT STRUCTURE AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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13335867
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Filing Dt:
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12/22/2011
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Publication #:
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Pub Dt:
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05/03/2012
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Title:
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Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor
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Patent #:
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Issue Dt:
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11/01/2016
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Application #:
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13336860
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Filing Dt:
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12/23/2011
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Publication #:
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Pub Dt:
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06/27/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING EXTENDED SEMICONDUCTOR DEVICE WITH FAN-OUT INTERCONNECT STRUCTURE TO REDUCE COMPLEXITY OF SUBSTRATE
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Issue Dt:
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02/11/2014
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13339185
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Filing Dt:
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12/28/2011
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Publication #:
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Pub Dt:
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05/03/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF SHIELDING SEMICONDUCTOR DIE FROM INTER-DEVICE INTERFERENCE
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Patent #:
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Issue Dt:
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07/15/2014
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Application #:
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13345589
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Filing Dt:
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01/06/2012
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Publication #:
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Pub Dt:
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05/03/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
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Patent #:
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Issue Dt:
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07/12/2016
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13346415
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Filing Dt:
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01/09/2012
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Publication #:
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Pub Dt:
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05/03/2012
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Title:
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Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring
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Patent #:
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Issue Dt:
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02/03/2015
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13349510
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Filing Dt:
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01/12/2012
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Publication #:
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Pub Dt:
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05/03/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED INTERCONNECT LAYER FOR STACKED SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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11/12/2013
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Application #:
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13349829
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Filing Dt:
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01/13/2012
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED EMI SHIELDING FRAME WITH CAVITIES CONTAINING PENETRABLE MATERIAL OVER SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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07/23/2013
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13349919
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Filing Dt:
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01/13/2012
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Publication #:
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Pub Dt:
|
05/10/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED EMI SHIELDING FRAME WITH CAVITIES CONTAINING PENETRABLE MATERIAL OVER SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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10/09/2012
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13350299
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01/13/2012
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED INTERCONNECT LAYER FOR STACKED SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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08/02/2016
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Application #:
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13350692
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Filing Dt:
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01/13/2012
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Publication #:
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Pub Dt:
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05/10/2012
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Title:
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SEMICONDUCTOR DEVICE INCLUDING PRE-FABRICATED SHIELDING FRAME DISPOSED OVER SEMICONDUCTOR DIE
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Issue Dt:
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03/19/2013
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13355354
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Filing Dt:
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01/20/2012
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Pub Dt:
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05/17/2012
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Title:
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METHOD OF FORMING TOP ELECTRODE FOR CAPACITOR AND INTERCONNECTION IN INTEGRATED PASSIVE DEVICE (IPD)
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Issue Dt:
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10/28/2014
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13356485
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01/23/2012
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Pub Dt:
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05/17/2012
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Title:
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Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure
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Issue Dt:
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12/03/2013
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Application #:
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13360549
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIAS IN PERIPHERAL REGION CONNECTING SHIELDING LAYER TO GROUND
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Patent #:
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Issue Dt:
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05/24/2016
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13365097
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02/02/2012
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Pub Dt:
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05/24/2012
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Title:
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Semiconductor Device and Method of Forming Passive Devices
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Patent #:
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Issue Dt:
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09/03/2013
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Application #:
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13366008
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Filing Dt:
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02/03/2012
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Publication #:
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Pub Dt:
|
05/23/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure
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Patent #:
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Issue Dt:
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09/03/2013
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Application #:
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13366008
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Filing Dt:
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02/03/2012
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Publication #:
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Pub Dt:
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05/23/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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13366560
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Filing Dt:
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02/06/2012
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Publication #:
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Pub Dt:
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05/31/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DIE
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13366768
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Filing Dt:
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02/06/2012
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Publication #:
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Pub Dt:
|
08/16/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINAL LOCKS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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13367214
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Filing Dt:
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02/06/2012
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Publication #:
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Pub Dt:
|
05/31/2012
| | | | |
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Title:
|
SOLDER JOINT FLIP CHIP INTERCONNECTION
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Patent #:
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|
Issue Dt:
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07/24/2012
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Application #:
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13397562
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Filing Dt:
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02/15/2012
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Publication #:
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Pub Dt:
|
06/14/2012
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
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Patent #:
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Issue Dt:
|
02/23/2016
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Application #:
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13403859
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Filing Dt:
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02/23/2012
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Publication #:
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Pub Dt:
|
06/21/2012
| | | | |
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Title:
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Semiconductor Device with Thin Profile WLCSP with Vertical Interconnect over Package Footprint
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Patent #:
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Issue Dt:
|
01/31/2017
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Application #:
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13403889
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Filing Dt:
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02/23/2012
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Publication #:
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Pub Dt:
|
06/21/2012
| | | | |
|
Title:
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Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint
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Patent #:
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Issue Dt:
|
06/03/2014
|
Application #:
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13405094
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Filing Dt:
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02/24/2012
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Publication #:
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Pub Dt:
|
06/21/2012
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING Z-INTERCONNECT CONDUCTIVE PILLARS WITH INNER POLYMER CORE
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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13408715
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Filing Dt:
|
02/29/2012
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|
Publication #:
|
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Pub Dt:
|
06/21/2012
| | | | |
|
Title:
|
Double-Sided Semiconductor Device and Method of Forming Top-Side and Bottom-Side Interconnect Structures
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Patent #:
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Issue Dt:
|
02/04/2014
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Application #:
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13417034
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Filing Dt:
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03/09/2012
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|
Publication #:
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|
Pub Dt:
|
09/12/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NON-LINEAR INTERCONNECT LAYER WITH EXTENDED LENGTH FOR JOINT RELIABILITY
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Patent #:
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Issue Dt:
|
02/04/2014
|
Application #:
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13417034
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Filing Dt:
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03/09/2012
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|
Publication #:
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|
Pub Dt:
|
09/12/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NON-LINEAR INTERCONNECT LAYER WITH EXTENDED LENGTH FOR JOINT RELIABILITY
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|
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Patent #:
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|
Issue Dt:
|
11/19/2013
|
Application #:
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13419242
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Filing Dt:
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03/13/2012
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|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
|
OPTICAL SEMICONDUCTOR DEVICE HAVING PRE-MOLDED LEADFRAME WITH WINDOW AND METHOD THEREFOR
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|
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Patent #:
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|
Issue Dt:
|
06/02/2015
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Application #:
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13420400
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Filing Dt:
|
03/14/2012
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|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING OPEN CAVITY IN TSV INTERPOSER TO CONTAIN SEMICONDUCTOR DIE IN WLCSMP
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|
|
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|
Patent #:
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|
Issue Dt:
|
06/02/2015
|
Application #:
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13420400
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Filing Dt:
|
03/14/2012
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|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING OPEN CAVITY IN TSV INTERPOSER TO CONTAIN SEMICONDUCTOR DIE IN WLCSMP
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|
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|
Patent #:
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|
Issue Dt:
|
07/02/2013
|
Application #:
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13421770
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Filing Dt:
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03/15/2012
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|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming With Three-Dimensional Vertically Oriented Integrated Capacitors
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|
Patent #:
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|
Issue Dt:
|
10/07/2014
|
Application #:
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13422649
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Filing Dt:
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03/16/2012
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|
Publication #:
|
|
Pub Dt:
|
09/19/2013
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND MOLDED CAVITIES AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
01/26/2016
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Application #:
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13422981
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Filing Dt:
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03/16/2012
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|
Publication #:
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|
Pub Dt:
|
09/19/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPLIANT CONDUCTIVE INTERCONNECT STRUCTURE IN FLIPCHIP PACKAGE
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|
Patent #:
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|
Issue Dt:
|
01/27/2015
|
Application #:
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13423262
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Filing Dt:
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03/18/2012
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|
Publication #:
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Pub Dt:
|
07/12/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
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|
Patent #:
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|
Issue Dt:
|
01/08/2013
|
Application #:
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13423263
|
Filing Dt:
|
03/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
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|
Patent #:
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|
Issue Dt:
|
06/20/2017
|
Application #:
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13423265
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Filing Dt:
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03/18/2012
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|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING IPD ON MOLDED SUBSTRATE
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|
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|
Patent #:
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|
Issue Dt:
|
05/21/2013
|
Application #:
|
13423739
|
Filing Dt:
|
03/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
|
Title:
|
SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING SAME
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|
|
|
Patent #:
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|
Issue Dt:
|
12/20/2016
|
Application #:
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13423782
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Filing Dt:
|
03/19/2012
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|
Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NO-FLOW UNDERFILL MATERIAL AROUND VERTICAL INTERCONNECT STRUCTURE
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|
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Patent #:
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|
Issue Dt:
|
08/20/2013
|
Application #:
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13423832
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Filing Dt:
|
03/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE
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|
|
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|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13423832
|
Filing Dt:
|
03/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE
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|
|
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|
Patent #:
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|
Issue Dt:
|
01/29/2019
|
Application #:
|
13424484
|
Filing Dt:
|
03/20/2012
|
|
Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for IPD and Baseband Circuit Separated by High-Resistivity Molding Compound
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13424710
|
Filing Dt:
|
03/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/12/2016
|
Application #:
|
13424968
|
Filing Dt:
|
03/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINALS AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13425277
|
Filing Dt:
|
03/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND LEADFRAME ETCHING AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/26/2016
|
Application #:
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13425286
|
Filing Dt:
|
03/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/02/2014
|
Application #:
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13425349
|
Filing Dt:
|
03/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE LAYER OVER METAL SUBSTRATE FOR ELECTRICAL INTERCONNECT OF SEMICONDUCTOR DIE
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|
Patent #:
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|
Issue Dt:
|
12/02/2014
|
Application #:
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13425349
|
Filing Dt:
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03/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE LAYER OVER METAL SUBSTRATE FOR ELECTRICAL INTERCONNECT OF SEMICONDUCTOR DIE
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|
Patent #:
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|
Issue Dt:
|
09/19/2017
|
Application #:
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13425768
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Filing Dt:
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03/21/2012
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|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF
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|
Patent #:
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|
Issue Dt:
|
01/20/2015
|
Application #:
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13426416
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Filing Dt:
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03/21/2012
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|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF SINGULATING SEMICONDUCTOR WAFER ALONG MODIFIED REGION WITHIN NON-ACTIVE REGION FORMED BY IRRADIATING ENERGY THROUGH MOUNTING TAPE
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|
Patent #:
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|
Issue Dt:
|
01/20/2015
|
Application #:
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13426416
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Filing Dt:
|
03/21/2012
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|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF SINGULATING SEMICONDUCTOR WAFER ALONG MODIFIED REGION WITHIN NON-ACTIVE REGION FORMED BY IRRADIATING ENERGY THROUGH MOUNTING TAPE
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|
Patent #:
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|
Issue Dt:
|
01/21/2014
|
Application #:
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13426442
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Filing Dt:
|
03/21/2012
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|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
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|
Patent #:
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|
Issue Dt:
|
05/06/2014
|
Application #:
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13426529
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Filing Dt:
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03/21/2012
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|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ULTRA-THIN CHIP AND METHOD OF MANUFACTURE THEREOF
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|
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|
Patent #:
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|
Issue Dt:
|
07/29/2014
|
Application #:
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13426552
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Filing Dt:
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03/21/2012
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|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO-VIAS PARTIALLY THROUGH INSULATING MATERIAL OVER BUMP INTERCONNECT CONDUCTIVE LAYER FOR STRESS RELIEF
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Patent #:
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|
Issue Dt:
|
07/29/2014
|
Application #:
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13426552
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Filing Dt:
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03/21/2012
|
|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO-VIAS PARTIALLY THROUGH INSULATING MATERIAL OVER BUMP INTERCONNECT CONDUCTIVE LAYER FOR STRESS RELIEF
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|
Patent #:
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|
Issue Dt:
|
12/02/2014
|
Application #:
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13426561
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Filing Dt:
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03/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR FORMING OPENINGS AND TRENCHES IN INSULATING LAYER BY FIRST LDA AND SECOND LDA FOR RDL FORMATION
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|
Patent #:
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|
Issue Dt:
|
12/02/2014
|
Application #:
|
13426561
|
Filing Dt:
|
03/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING OPENINGS AND TRENCHES IN INSULATING LAYER BY FIRST LDA AND SECOND LDA FOR RDL FORMATION
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|
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|
Patent #:
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|
Issue Dt:
|
12/30/2014
|
Application #:
|
13426576
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Filing Dt:
|
03/21/2012
|
|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Simultaneous Testing of Multiple Interconnects for Electro-Migration
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|
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|
Patent #:
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|
Issue Dt:
|
12/30/2014
|
Application #:
|
13426576
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Filing Dt:
|
03/21/2012
|
|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Simultaneous Testing of Multiple Interconnects for Electro-Migration
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13427221
|
Filing Dt:
|
03/22/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/23/2014
|
Application #:
|
13427598
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Filing Dt:
|
03/22/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME LEAD ARRAY ROUTING AND METHOD OF MANUFACTURE THEREOF
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|
Patent #:
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|
Issue Dt:
|
10/24/2017
|
Application #:
|
13428251
|
Filing Dt:
|
03/23/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A GRID ARRAY WITH A LEADFRAME AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/14/2015
|
Application #:
|
13428439
|
Filing Dt:
|
03/23/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13429119
|
Filing Dt:
|
03/23/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
SEMICONDUCTOR METHOD AND DEVICE OF FORMING A FAN-OUT POP DEVICE WITH PWB VERTICAL INTERCONNECT UNITS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13429119
|
Filing Dt:
|
03/23/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
SEMICONDUCTOR METHOD AND DEVICE OF FORMING A FAN-OUT POP DEVICE WITH PWB VERTICAL INTERCONNECT UNITS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
13430538
|
Filing Dt:
|
03/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13430577
|
Filing Dt:
|
03/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices
|
|
