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Patent #:
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Issue Dt:
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12/06/2016
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Application #:
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13682281
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Filing Dt:
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11/20/2012
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Publication #:
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Pub Dt:
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03/28/2013
| | | | |
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Title:
|
SEMICONDUCTOR PACKAGE AND METHOD OF FORMING Z-DIRECTION CONDUCTIVE POSTS EMBEDDED IN STRUCTURALLY PROTECTIVE ENCAPSULANT
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Patent #:
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Issue Dt:
|
08/16/2016
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Application #:
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13682510
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Filing Dt:
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11/20/2012
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Publication #:
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Pub Dt:
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03/28/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Insulating Layer on Conductive Traces for Electrical Isolation in Fine Pitch Bonding
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Patent #:
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Issue Dt:
|
08/04/2015
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Application #:
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13683884
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Filing Dt:
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11/21/2012
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Publication #:
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Pub Dt:
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03/28/2013
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS EMBEDDED IN PHOTOSENSITIVE ENCAPSULANT
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Patent #:
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Issue Dt:
|
06/23/2015
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Application #:
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13683946
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Filing Dt:
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11/21/2012
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Publication #:
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Pub Dt:
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05/02/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS AND HEAT SINK OVER SEMICONDUCTOR DIE USING LEADFRAME
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Patent #:
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Issue Dt:
|
06/23/2015
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Application #:
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13683946
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Filing Dt:
|
11/21/2012
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Publication #:
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Pub Dt:
|
05/02/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS AND HEAT SINK OVER SEMICONDUCTOR DIE USING LEADFRAME
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Patent #:
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Issue Dt:
|
11/25/2014
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Application #:
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13684055
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Filing Dt:
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11/21/2012
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Publication #:
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Pub Dt:
|
03/28/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING DIFFERENT HEIGHT CONDUCTIVE PILLARS TO ELECTRICALLY INTERCONNECT STACKED LATERALLY OFFSET SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
|
08/27/2013
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Application #:
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13691427
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
|
04/11/2013
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE INCLUDING BUMP FORMED ON SUBSTRATE TO PREVENT EXTRIMELY-LOW DIELECTRIC CONSTANT (ELK) INTERLAYER DIELECTRIC LAYER (ILD) DELAMINATION DURING REFLOW PROCESS
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Patent #:
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Issue Dt:
|
12/09/2014
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Application #:
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13691440
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
|
04/11/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die
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Patent #:
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Issue Dt:
|
10/06/2015
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Application #:
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13691464
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
|
04/11/2013
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED MULTI-DIE LEADFRAME FOR ELECTRICAL INTERCONNECT OF STACKED SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
|
04/22/2014
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Application #:
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13691578
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
|
04/11/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Conductive TSV With Insulating Annular Ring
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Patent #:
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|
Issue Dt:
|
09/10/2013
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Application #:
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13706818
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Filing Dt:
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12/06/2012
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|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AIR GAP ADJACENT TO STRESS SENSITIVE REGION OF THE DIE
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Patent #:
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Issue Dt:
|
01/13/2015
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Application #:
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13714061
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Filing Dt:
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12/13/2012
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Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME ELECTRICALLY CONNECTED TO EMBEDDED SEMICONDUCTOR DIE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13714815
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Filing Dt:
|
12/14/2012
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|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE GRID ARRAY LEAD FRAME
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|
Patent #:
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|
Issue Dt:
|
04/26/2016
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Application #:
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13714865
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Filing Dt:
|
12/14/2012
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|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSFERABLE TRACE LEAD FRAME
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Patent #:
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|
Issue Dt:
|
01/19/2016
|
Application #:
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13715424
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Filing Dt:
|
12/14/2012
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|
Publication #:
|
|
Pub Dt:
|
11/06/2014
| | | | |
|
Title:
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Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect
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|
Patent #:
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|
Issue Dt:
|
11/01/2016
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Application #:
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13716799
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Filing Dt:
|
12/17/2012
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|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Directional RF Coupler with IPD for Additional RF Signal Processing
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|
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|
Patent #:
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|
Issue Dt:
|
10/04/2016
|
Application #:
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13720516
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Filing Dt:
|
12/19/2012
|
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Reduced Surface Roughness in Molded Underfill for Improved C-SAM Inspection
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|
Patent #:
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|
Issue Dt:
|
09/04/2018
|
Application #:
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13726467
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Filing Dt:
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12/24/2012
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|
Publication #:
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|
Pub Dt:
|
06/06/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY IN BUILD-UP INTERCONNECT STRUCTURE FOR SHORT SIGNAL PATH BETWEEN DIE
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|
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|
Patent #:
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|
Issue Dt:
|
06/03/2014
|
Application #:
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13727116
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Filing Dt:
|
12/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
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|
|
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|
Patent #:
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Issue Dt:
|
06/03/2014
|
Application #:
|
13727116
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Filing Dt:
|
12/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
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|
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|
Patent #:
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Issue Dt:
|
12/13/2016
|
Application #:
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13728012
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Filing Dt:
|
12/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS
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Patent #:
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Issue Dt:
|
12/30/2014
|
Application #:
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13732150
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Filing Dt:
|
12/31/2012
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|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die
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|
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|
Patent #:
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|
Issue Dt:
|
12/30/2014
|
Application #:
|
13732150
|
Filing Dt:
|
12/31/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die
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|
|
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|
Patent #:
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|
Issue Dt:
|
03/24/2015
|
Application #:
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13740151
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Filing Dt:
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01/11/2013
|
|
Publication #:
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|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF
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|
Patent #:
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|
Issue Dt:
|
03/10/2015
|
Application #:
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13742580
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Filing Dt:
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01/16/2013
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CORELESS SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
07/07/2015
|
Application #:
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13743054
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Filing Dt:
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01/16/2013
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|
Publication #:
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|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Through-Silicon-Via with Sacrificial Layer
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|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13750975
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Filing Dt:
|
01/25/2013
|
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Title:
|
METHOD OF FORMING A BUMP-ON-LEAD FLIP CHIP INTERCONNECTION HAVING HIGHER ESCAPE ROUTING DENSITY
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Patent #:
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Issue Dt:
|
09/17/2013
|
Application #:
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13752157
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Filing Dt:
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01/28/2013
|
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPOSITE BUMP-ON-LEAD INTERCONNECTION
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Patent #:
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Issue Dt:
|
11/05/2013
|
Application #:
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13756679
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Filing Dt:
|
02/01/2013
|
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK
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Patent #:
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|
Issue Dt:
|
10/08/2013
|
Application #:
|
13756779
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Filing Dt:
|
02/01/2013
|
|
Title:
|
Bump-On-Lead Flip Chip Interconnection
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|
Patent #:
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|
Issue Dt:
|
02/11/2014
|
Application #:
|
13756817
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Filing Dt:
|
02/01/2013
|
|
Title:
|
SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE
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|
Patent #:
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Issue Dt:
|
11/26/2013
|
Application #:
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13756905
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Filing Dt:
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02/01/2013
|
|
Title:
|
SOLDER JOINT FLIP CHIP INTERCONNECTION
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|
Patent #:
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Issue Dt:
|
04/19/2016
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Application #:
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13759911
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Filing Dt:
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02/05/2013
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Publication #:
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|
Pub Dt:
|
08/07/2014
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING STRESS RELIEVING VIAS FOR IMPROVED FAN-OUT WLCSP PACKAGE
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Patent #:
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Issue Dt:
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05/12/2015
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Application #:
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13760187
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Filing Dt:
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02/06/2013
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Publication #:
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|
Pub Dt:
|
06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL
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Patent #:
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Issue Dt:
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05/12/2015
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Application #:
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13760187
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Filing Dt:
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02/06/2013
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Publication #:
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Pub Dt:
|
06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL
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Patent #:
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Issue Dt:
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04/22/2014
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Application #:
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13765478
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Filing Dt:
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02/12/2013
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Publication #:
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|
Pub Dt:
|
07/04/2013
| | | | |
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Title:
|
Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
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Patent #:
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Issue Dt:
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04/22/2014
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Application #:
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13765478
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Filing Dt:
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02/12/2013
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|
Publication #:
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Pub Dt:
|
07/04/2013
| | | | |
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Title:
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Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
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Patent #:
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Issue Dt:
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01/12/2016
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Application #:
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13765594
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Filing Dt:
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02/12/2013
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Publication #:
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|
Pub Dt:
|
06/20/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECT STRUCTURE ON LEADFRAME
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Patent #:
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Issue Dt:
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11/04/2014
|
Application #:
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13766493
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Filing Dt:
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02/13/2013
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Publication #:
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|
Pub Dt:
|
06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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11/04/2014
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Application #:
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13766493
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Filing Dt:
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02/13/2013
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Publication #:
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Pub Dt:
|
06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
|
10/21/2014
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Application #:
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13766646
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Filing Dt:
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02/13/2013
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Publication #:
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Pub Dt:
|
06/20/2013
| | | | |
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Title:
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LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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13766646
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Filing Dt:
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02/13/2013
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Publication #:
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|
Pub Dt:
|
06/20/2013
| | | | |
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Title:
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LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT
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Patent #:
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Issue Dt:
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04/29/2014
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Application #:
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13768862
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Filing Dt:
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02/15/2013
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Publication #:
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|
Pub Dt:
|
06/20/2013
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
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Patent #:
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Issue Dt:
|
04/29/2014
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Application #:
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13768862
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Filing Dt:
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02/15/2013
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Publication #:
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Pub Dt:
|
06/20/2013
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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13769302
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Filing Dt:
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02/16/2013
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Publication #:
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|
Pub Dt:
|
08/08/2013
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOLDING
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Patent #:
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Issue Dt:
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09/16/2014
|
Application #:
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13769302
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Filing Dt:
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02/16/2013
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|
Publication #:
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|
Pub Dt:
|
08/08/2013
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOLDING
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Patent #:
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Issue Dt:
|
01/30/2018
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Application #:
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13771825
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Filing Dt:
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02/20/2013
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Publication #:
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|
Pub Dt:
|
09/12/2013
| | | | |
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Title:
|
Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application Processor and Memory Integration
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Patent #:
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Issue Dt:
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03/22/2016
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Application #:
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13772683
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Filing Dt:
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02/21/2013
|
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Publication #:
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|
Pub Dt:
|
09/05/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING A LOW PROFILE EMBEDDED WAFER LEVEL BALL GRID ARRAY MOLDED LASER PACKAGE (EWLB-MLP)
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Patent #:
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Issue Dt:
|
06/24/2014
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Application #:
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13782618
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Filing Dt:
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03/01/2013
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Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
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Patent #:
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Issue Dt:
|
06/24/2014
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Application #:
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13782618
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Filing Dt:
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03/01/2013
|
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
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Patent #:
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Issue Dt:
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09/20/2016
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Application #:
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13782939
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Filing Dt:
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03/01/2013
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Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
|
Title:
|
Integrated Passive Devices
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Patent #:
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|
Issue Dt:
|
07/29/2014
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Application #:
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13791375
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Filing Dt:
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03/08/2013
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|
Publication #:
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|
Pub Dt:
|
10/03/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
07/29/2014
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Application #:
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13791375
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Filing Dt:
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03/08/2013
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|
Publication #:
|
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Pub Dt:
|
10/03/2013
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
04/05/2016
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Application #:
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13795679
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Filing Dt:
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03/12/2013
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Publication #:
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Pub Dt:
|
02/27/2014
| | | | |
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Title:
|
Semiconductor Device and Method of Forming RDL Using UV-Cured Conductive Ink Over Wafer Level Package
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Patent #:
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Issue Dt:
|
01/31/2017
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Application #:
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13800807
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Filing Dt:
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03/13/2013
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Publication #:
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Pub Dt:
|
03/20/2014
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF USING SUBSTRATE HAVING BASE AND CONDUCTIVE POSTS TO FORM VERTICAL INTERCONNECT STRUCTURE IN EMBEDDED DIE PACKAGE
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Patent #:
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Issue Dt:
|
05/24/2016
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Application #:
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13801294
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Filing Dt:
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03/13/2013
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
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Title:
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Semiconductor Device and Method of Forming WLCSP with Semiconductor Die Embedded within Interconnect Structure
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Patent #:
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Issue Dt:
|
10/24/2017
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Application #:
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13801675
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Filing Dt:
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03/13/2013
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF USING PARTIAL WAFER SINGULATION FOR IMPROVED WAFER LEVEL EMBEDDED SYSTEM IN PACKAGE
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Patent #:
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Issue Dt:
|
07/05/2016
|
Application #:
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13832118
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Filing Dt:
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03/15/2013
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Publication #:
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Pub Dt:
|
03/20/2014
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over Carrier for Testing at Interim Stages
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Patent #:
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Issue Dt:
|
01/29/2019
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Application #:
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13832205
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Filing Dt:
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03/15/2013
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Publication #:
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Pub Dt:
|
03/20/2014
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Dual-Sided Interconnect Structures in FO-WLCSP
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|
Patent #:
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|
Issue Dt:
|
06/23/2015
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Application #:
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13832333
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Filing Dt:
|
03/15/2013
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|
Publication #:
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|
Pub Dt:
|
08/08/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
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Patent #:
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Issue Dt:
|
05/22/2018
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Application #:
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13832449
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Filing Dt:
|
03/15/2013
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|
Publication #:
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|
Pub Dt:
|
03/20/2014
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DUAL-SIDED INTERCONNECT STRUCTURES IN FO-WLCSP
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Patent #:
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Issue Dt:
|
09/13/2016
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Application #:
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13832781
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Filing Dt:
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03/15/2013
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Publication #:
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Pub Dt:
|
03/20/2014
| | | | |
|
Title:
|
Semiconductor Device having Wire Studs as Vertical Interconnect in FO-WLP
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|
Patent #:
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|
Issue Dt:
|
11/15/2016
|
Application #:
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13832809
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Filing Dt:
|
03/15/2013
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|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
|
Title:
|
Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP
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|
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|
Patent #:
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|
Issue Dt:
|
07/29/2014
|
Application #:
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13845329
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Filing Dt:
|
03/18/2013
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|
Publication #:
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|
Pub Dt:
|
08/15/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure
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|
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|
Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
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13845329
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Filing Dt:
|
03/18/2013
|
|
Publication #:
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|
Pub Dt:
|
08/15/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure
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|
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|
Patent #:
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|
Issue Dt:
|
12/20/2016
|
Application #:
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13845409
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Filing Dt:
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03/18/2013
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|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
|
Title:
|
PACKAGE-IN-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS
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|
Patent #:
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|
Issue Dt:
|
06/13/2017
|
Application #:
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13845542
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Filing Dt:
|
03/18/2013
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|
Publication #:
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|
Pub Dt:
|
08/22/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP
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|
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|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
13846014
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Filing Dt:
|
03/18/2013
|
|
Publication #:
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|
Pub Dt:
|
08/22/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE LEADS FROM BASE SUBSTRATE AS STANDOFF FOR STACKING SEMICONDUCTOR DIE
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|
Patent #:
|
|
Issue Dt:
|
03/08/2016
|
Application #:
|
13846593
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Filing Dt:
|
03/18/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF CALIBRATING WARPAGE TESTING SYSTEM TO ACCURATELY MEASURE SEMICONDUCTOR PACKAGE WARPAGE
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|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13846742
|
Filing Dt:
|
03/18/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13846742
|
Filing Dt:
|
03/18/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13853810
|
Filing Dt:
|
03/29/2013
|
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
|
Title:
|
Methods of Manufacturing Flip Chip Semiconductor Packages Using Double-Sided Thermal Compression Bonding
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
13853969
|
Filing Dt:
|
03/29/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DIE WITH ACTIVE REGION RESPONSIVE TO EXTERNAL STIMULUS
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|
Patent #:
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|
Issue Dt:
|
11/25/2014
|
Application #:
|
13870928
|
Filing Dt:
|
04/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13870928
|
Filing Dt:
|
04/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
13871157
|
Filing Dt:
|
04/26/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/19/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING COVER TO SEMICONDUCTOR DIE AND INTERPOSER WITH ADHESIVE MATERIAL
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|
Patent #:
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Issue Dt:
|
01/23/2018
|
Application #:
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13874150
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Filing Dt:
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04/30/2013
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|
Publication #:
|
|
Pub Dt:
|
09/19/2013
| | | | |
|
Title:
|
Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers
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|
Patent #:
|
|
Issue Dt:
|
09/20/2016
|
Application #:
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13886556
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Filing Dt:
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05/03/2013
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Publication #:
|
|
Pub Dt:
|
09/19/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die
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|
Patent #:
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|
Issue Dt:
|
03/31/2015
|
Application #:
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13887180
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Filing Dt:
|
05/03/2013
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|
Publication #:
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|
Pub Dt:
|
09/19/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Interposer and Opposing Build-Up Interconnect Structure with Connecting Conductive TMV for Electrical Interconnect of FO-WLCSP
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|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13887180
|
Filing Dt:
|
05/03/2013
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|
Publication #:
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|
Pub Dt:
|
09/19/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Interposer and Opposing Build-Up Interconnect Structure with Connecting Conductive TMV for Electrical Interconnect of FO-WLCSP
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|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13893616
|
Filing Dt:
|
05/14/2013
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|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
METHOD OF FORMING RDL WIDER THAN CONTACT PAD ALONG FIRST AXIS AND NARROWER THAN CONTACT PAD ALONG SECOND
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|
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|
Patent #:
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|
Issue Dt:
|
02/24/2015
|
Application #:
|
13893616
|
Filing Dt:
|
05/14/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
METHOD OF FORMING RDL WIDER THAN CONTACT PAD ALONG FIRST AXIS AND NARROWER THAN CONTACT PAD ALONG SECOND
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|
|
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|
Patent #:
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|
Issue Dt:
|
08/19/2014
|
Application #:
|
13896608
|
Filing Dt:
|
05/17/2013
|
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED LEADS AND METHOD OF MANUFACTURE THEREOF
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|
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|
|
Patent #:
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|
Issue Dt:
|
01/13/2015
|
Application #:
|
13896635
|
Filing Dt:
|
05/17/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die
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|
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|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13896635
|
Filing Dt:
|
05/17/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die
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|
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|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13905845
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Filing Dt:
|
05/30/2013
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|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF CONFINING CONDUCTIVE BUMP MATERIAL DURING REFLOW WITH SOLDER MASK PATCH
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|
Patent #:
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Issue Dt:
|
06/03/2014
|
Application #:
|
13905845
|
Filing Dt:
|
05/30/2013
|
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF CONFINING CONDUCTIVE BUMP MATERIAL DURING REFLOW WITH SOLDER MASK PATCH
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13906060
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Filing Dt:
|
05/30/2013
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|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Reconstituted Wafer With Larger Carrier to Achieve More EWLB Packages Per Wafer with Encapsulant Deposited Under Temperature and Pressure
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13906489
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Filing Dt:
|
05/31/2013
|
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Protective Coating Material Over Semiconductor Wafer to Reduce Lamination Tape Residue
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|
Patent #:
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|
Issue Dt:
|
02/09/2016
|
Application #:
|
13906667
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Filing Dt:
|
05/31/2013
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|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED HEAT SPREADER FRAME WITH EMBEDDED SEMICONDUCTOR DIE
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|
Patent #:
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|
Issue Dt:
|
11/11/2014
|
Application #:
|
13906844
|
Filing Dt:
|
05/31/2013
|
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH BUMP FORMED ON SUBSTRATE TO PREVENT ELK ILD DELAMINATION DURING REFLOW PROCESS
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|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13906844
|
Filing Dt:
|
05/31/2013
|
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH BUMP FORMED ON SUBSTRATE TO PREVENT ELK ILD DELAMINATION DURING REFLOW PROCESS
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|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
13910786
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Filing Dt:
|
06/05/2013
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|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
|
Title:
|
SYSTEM-IN-PACKAGE HAVING INTEGRATED PASSIVE DEVICES AND METHOD THEREFOR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2017
|
Application #:
|
13917982
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Filing Dt:
|
06/14/2013
|
|
Publication #:
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|
Pub Dt:
|
10/24/2013
| | | | |
|
Title:
|
Semiconductor Method and Device of Forming a Fan-Out Device with PWB Vertical Interconnect Units
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|
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|
Patent #:
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|
Issue Dt:
|
02/23/2016
|
Application #:
|
13918103
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Filing Dt:
|
06/14/2013
|
|
Publication #:
|
|
Pub Dt:
|
04/02/2015
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MAKING AN EMBEDDED WAFER LEVEL BALL GRID ARRAY (EWLB) PACKAGE ON PACKAGE (POP) DEVICE WITH A SLOTTED METAL CARRIER INTERPOSER
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|
Patent #:
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|
Issue Dt:
|
03/28/2017
|
Application #:
|
13928754
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Filing Dt:
|
06/27/2013
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2015
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED PAD ON LAYERED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2016
|
Application #:
|
13928862
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Filing Dt:
|
06/27/2013
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2015
| | | | |
|
Title:
|
Semiconductor Device and Method of Individual Die Bonding Followed by Simultaneous Multiple Die Thermal Compression Bonding
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13929426
|
Filing Dt:
|
06/27/2013
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2015
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming an Interposer Including a Beveled Edge
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/18/2017
|
Application #:
|
13929485
|
Filing Dt:
|
06/27/2013
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2015
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Trench and Disposing Semiconductor Die Over Substrate to Control Outward Flow of Underfill Material
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13929767
|
Filing Dt:
|
06/27/2013
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2015
| | | | |
|
Title:
|
Methods of Forming Conductive Materials on Contact Pads
|
|
