|
Total properties:
66
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09200002
|
Filing Dt:
|
11/25/1998
|
|
Title:
|
ROW DECODER FOR A FLASH-EEPROM MEMORY DEVICE WITH THE POSSIBILITY OF SELECTIVE ERASING OF A SUB-GROUP OF ROWS OF A SECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09322460
|
Filing Dt:
|
05/28/1999
|
|
Title:
|
DEVICE AND METHOD FOR READING NONVOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
09324087
|
Filing Dt:
|
06/01/1999
|
|
Title:
|
LINE DECODER FOR A LOW SUPPLY VOLTAGE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09359923
|
Filing Dt:
|
07/22/1999
|
|
Title:
|
METHOD FOR MANUFACTURING ELECTRONIC DEVICES HAVING HV TRANSISTORS AND LV TRANSISTORS WITH SALICIDED JUNCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09392937
|
Filing Dt:
|
09/09/1999
|
|
Title:
|
METHOD FOR MANUFACTURING ELECTRONIC DEVICES COMPRISING NON-VOLATILE MEMORY CELLS AND LV TRANSISTORS WITH SALICIDED JUNCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09469849
|
Filing Dt:
|
12/21/1999
|
|
Title:
|
METHOD FOR MANUFACTURING ELECTRONIC DEVICES, COMPRISING NON-SALICIDED NON-VOLATILE MEMORY CELLS, NON-SALICIDED HV TRANSISTORS, AND LV TRANSISTORS WITH SALICIDED JUNCTIONS WITH FEW MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09513598
|
Filing Dt:
|
02/25/2000
|
|
Title:
|
Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09599356
|
Filing Dt:
|
06/21/2000
|
|
Title:
|
Flash compatible EEPROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09627273
|
Filing Dt:
|
07/28/2000
|
|
Title:
|
SINGLE SUPPLY VOLTAGE NONVOLATILE MEMORY DEVICE WITH ROW DECODING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09631187
|
Filing Dt:
|
08/02/2000
|
|
Title:
|
METHOD FOR PROGRAMMING MULTI-LEVEL NON-VOLATILE MEMORIES BY CONTROLLING THE GATE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09670471
|
Filing Dt:
|
09/26/2000
|
|
Title:
|
Memory test method and nonvolatile memory with low error masking probability
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09699309
|
Filing Dt:
|
10/27/2000
|
|
Title:
|
METHOD FOR CONTROLLED SOFT PROGRAMMING OF NON-VOLATILE MEMORY CELLS, IN PARTICULAR OF THE FLASH EEPROM AND EPROM TYPE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09713144
|
Filing Dt:
|
11/14/2000
|
|
Title:
|
PROCESS FOR MANUFACTURING ELECTRONIC DEVICES COMPRISING HIGH VOLTAGE MOS TRANSISTORS, AND ELECTRONIC DEVICE THUS OBTAINED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
09718971
|
Filing Dt:
|
11/22/2000
|
|
Title:
|
PROCESS FOR MANUFACTURING ELECTRONIC DEVICES COMPRISING NONVOLATILE MEMORY CELLS OF REDUCED DIMENSIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
09773760
|
Filing Dt:
|
01/31/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2001
| | | | |
|
Title:
|
ATD GENERATION IN A SYNCHRONOUS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09774542
|
Filing Dt:
|
01/31/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2001
| | | | |
|
Title:
|
INTERLEAVED DATA PATH AND OUTPUT MANAGEMENT ARCHITECTURE FOR AN INTERLEAVED MEMORY AND LOAD PULSER CIRCUIT FOR OUTPUTTING THE READ DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09817363
|
Filing Dt:
|
03/20/2001
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2001
| | | | |
|
Title:
|
STRING PROGRAMMABLE NONVOLATILE MEMORY WITH NOR ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09930875
|
Filing Dt:
|
08/15/2001
|
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
|
Title:
|
DIRECT-COMPARISON READING CIRCUIT FOR A NONVOLATILE MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
09976473
|
Filing Dt:
|
10/11/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2002
| | | | |
|
Title:
|
METHOD FOR STORING AND READING DATA IN A MULTILEVEL NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
09977561
|
Filing Dt:
|
10/15/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2002
| | | | |
|
Title:
|
INTERLACED MEMORY DEVICE WITH RANDOM OR SEQUENTIAL ACCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2003
|
Application #:
|
10035909
|
Filing Dt:
|
12/19/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/29/2002
| | | | |
|
Title:
|
METHOD FOR STORING DATA IN A NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2003
|
Application #:
|
10118660
|
Filing Dt:
|
04/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2002
| | | | |
|
Title:
|
READING CIRCUIT AND METHOD FOR A MULTILEVEL NON-VOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10119523
|
Filing Dt:
|
04/09/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2002
| | | | |
|
Title:
|
METHOD FOR PROGRAMMING NONVOLATILE MEMORY CELLS WITH PROGRAM AND VERIFY ALGORITHM USING A STAIRCASE VOLTAGE WITH VARYING STEP AMPLITUDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2004
|
Application #:
|
10133231
|
Filing Dt:
|
04/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2002
| | | | |
|
Title:
|
METHOD AND CIRCUIT FOR GENERATING REFERENCE VOLTAGES FOR READING A MULTILEVEL MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10159780
|
Filing Dt:
|
05/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
METHOD FOR ERASING AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE, AND AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2003
|
Application #:
|
10225315
|
Filing Dt:
|
08/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
|
Title:
|
PROCESS FOR MANUFACTURING ELECTRONIC DEVICES COMPRISING NONVOLATILE MEMORY CELLS OF REDUCED DIMENSIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2004
|
Application #:
|
10259252
|
Filing Dt:
|
09/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
METHOD FOR STORING AND READING DATA IN A MULTILEVEL NONVOLATILE MEMORY, AND ARCHITECTURE THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
10639240
|
Filing Dt:
|
08/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/08/2004
| | | | |
|
Title:
|
NONVOLATILE STORAGE DEVICE AND SELF-REDUNDANCY METHOD FOR THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10657801
|
Filing Dt:
|
09/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
ION-IMPLANTATION MACHINE, CONTROL METHOD THEREOF, AND PROCESS FOR MANUFACTURING INTEGRATED DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10672293
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
INTEGRATED RESISTIVE ELEMENTS WITH SILICIDATION PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10700322
|
Filing Dt:
|
11/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
METHOD AND DEVICE FOR TIMING RANDOM READING OF A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
10713538
|
Filing Dt:
|
11/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
|
Title:
|
SELF-ALIGNED INTEGRATED ELECTRONIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10727478
|
Filing Dt:
|
12/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2005
|
Application #:
|
10734389
|
Filing Dt:
|
12/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
METHOD FOR FORMING BIT LINE OF FLASH DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10734533
|
Filing Dt:
|
12/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10736719
|
Filing Dt:
|
12/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
HIGH VOLTAGE TRANSFER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10739649
|
Filing Dt:
|
12/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/16/2004
| | | | |
|
Title:
|
METHOD OF MANUFACTURING DUAL GATE OXIDE FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10740089
|
Filing Dt:
|
12/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10740100
|
Filing Dt:
|
12/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
METHOD FOR READING FLASH MEMORY CELL, NAND-TYPE FLASH MEMORY APPARATUS, AND NOR-TYPE FLASH MEMORY APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10744495
|
Filing Dt:
|
12/23/2003
|
|
Title:
|
METHOD OF FORMING GATE ELECTRODE IN FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10745295
|
Filing Dt:
|
12/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
|
Title:
|
MOS DEVICE AND PROCESS FOR MANUFACTURING MOS DEVICES USING DUAL-POLYSILICON LAYER TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10745297
|
Filing Dt:
|
12/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
|
Title:
|
MOS DEVICE AND A PROCESS FOR MANUFACTURING MOS DEVICES USING A DUAL-POLYSILICON LAYER TECHNOLOGY WITH SIDE CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
10850834
|
Filing Dt:
|
05/21/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
ANALYSIS OF THE QUALITY OF CONTACTS AND VIAS IN MULTI-METAL FABRICATION PROCESSES OF SEMICONDUCTOR DEVICES, METHOD AND TEST CHIP ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10872725
|
Filing Dt:
|
06/21/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10878273
|
Filing Dt:
|
06/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
HIGH VOLTAGE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10878811
|
Filing Dt:
|
06/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
|
Title:
|
METHOD OF FORMING METAL LINE IN SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10879434
|
Filing Dt:
|
06/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
|
Title:
|
CIRCUIT OF REDUNDANCY IO FUSE IN SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10879848
|
Filing Dt:
|
06/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
HIGH VOLTAGE SWITCH CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10883279
|
Filing Dt:
|
06/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
10886003
|
Filing Dt:
|
07/07/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
METHOD OF GENERATING AN ENABLE SIGNAL OF A STANDARD MEMORY CORE AND RELATIVE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11089942
|
Filing Dt:
|
03/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/27/2005
| | | | |
|
Title:
|
NONLITHOGRAPHIC METHOD OF DEFINING GEOMETRIES FOR PLASMA AND/OR ION IMPLANTATION TREATMENTS ON A SEMICONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
11120766
|
Filing Dt:
|
05/03/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
CIRCUIT FOR SELECTING/DESELECTING A BITLINE OF A NON-VOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
11121615
|
Filing Dt:
|
05/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
METHOD AND CIRCUIT FOR VERIFYING AND EVENTUALLY SUBSTITUTING DEFECTIVE REFERENCE CELLS OF A MEMORY
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11152675
|
Filing Dt:
|
06/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
|
Title:
|
METHOD FOR MANAGING BAD MEMORY BLOCKS IN A NONVOLATILE MEMORY DEVICE, AND NONVOLATILE-MEMORY DEVICE IMPLEMENTING THE MANAGEMENT METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11178240
|
Filing Dt:
|
07/08/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
|
Title:
|
READ/VERIFY CIRCUIT FOR MULTILEVEL MEMORY CELLS WITH RAMP READ VOLTAGE, AND READ/VERIFY METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
11238137
|
Filing Dt:
|
09/28/2005
|
|
Publication #:
|
|
Pub Dt:
|
04/13/2006
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|
Title:
|
READING CIRCUIT AND METHOD FOR A NONVOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11270308
|
Filing Dt:
|
11/09/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
|
Title:
|
CHARGE-PUMP DEVICE WITH INCREASED CURRENT OUTPUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
11279663
|
Filing Dt:
|
04/13/2006
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
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|
Title:
|
METHOD AND CIRCUIT FOR SIMULTANEOUSLY PROGRAMMING MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11334205
|
Filing Dt:
|
01/18/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
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|
Title:
|
CONTROL OF VOLTAGES DURING ERASE AND RE-PROGRAM OPERATIONS OF MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
11337030
|
Filing Dt:
|
01/20/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
|
Title:
|
CIRCUIT FOR GENERATING AN INTERNAL ENABLING SIGNAL FOR AN OUTPUT BUFFER OF A MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
11381426
|
Filing Dt:
|
05/03/2006
|
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
|
Title:
|
RAMP GENERATOR AND RELATIVE ROW DECODER FOR FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
11460531
|
Filing Dt:
|
07/27/2006
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
|
Title:
|
NONVOLATILE MEMORY DEVICE WITH MULTIPLE REFERENCES AND CORRESPONDING CONTROL METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
11648838
|
Filing Dt:
|
12/28/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
|
Title:
|
PROCESS FOR DIGGING A DEEP TRENCH IN A SEMICONDUCTOR BODY AND SEMICONDUCTOR BODY SO OBTAINED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
11686133
|
Filing Dt:
|
03/14/2007
|
|
Publication #:
|
|
Pub Dt:
|
09/20/2007
| | | | |
|
Title:
|
SYNCHRONIZATION OF OPERATIONS IN DISTINCT MEMORY PARTITIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2009
|
Application #:
|
11687353
|
Filing Dt:
|
03/16/2007
|
|
Publication #:
|
|
Pub Dt:
|
09/20/2007
| | | | |
|
Title:
|
REDUCTION OF THE TIME FOR EXECUTING AN EXTERNALLY COMMANDED TRANSFER OF DATA IN AN INTEGRATED DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
11780581
|
Filing Dt:
|
07/20/2007
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
|
Title:
|
MEMORY DEVICE WITH FAIL SEARCH AND REDUNDANCY
|
|
