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Total properties:
19
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09286127
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Filing Dt:
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04/02/1999
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Title:
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CONFIGURABLE I/O CIRCUITRY DEFINING VIRTUAL PORTS
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09414322
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Filing Dt:
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10/06/1999
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Title:
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DIGITAL MULTIPLY-ACCUMULATE CIRCUIT THAT CAN OPERATE ON BOTH INTEGER AND FLOATING POINT NUMBERS SIMULTANEOUSLY
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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09543806
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Filing Dt:
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04/06/2000
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Title:
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GLOBAL BUS SYNCHRONOUS TRANSACTION ACKNOWLEDGE WITH NONRESPONSE DETECTION
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09679962
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Filing Dt:
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10/05/2000
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Title:
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Risc processor using register codes for expanded instruction set
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09680652
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Filing Dt:
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10/06/2000
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Title:
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MULTIPROCESSOR COMPUTER SYSTEMS WITH COMMAND FIFO BUFFER AT EACH TARGET DEVICE
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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09968097
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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BUS ARBITRATION SYSTEM AND METHOD FOR CARRYING OUT A CENTRALIZED ARBITRATION WITH INDEPENDENT BUS REQUEST AND GRANT LINES
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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09968581
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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REPROGRAMMABLE INPUT-OUTPUT PINS FOR FORMING DIFFERENT CHIP OR BOARD INTERFACES
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10061500
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Filing Dt:
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02/01/2002
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Title:
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COMBINED CYCLIC REDUNDANCY CHECK (CRC) AND REED-SOLOMON (RS) ERROR CHECKING UNIT
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10061543
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Filing Dt:
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02/01/2002
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Title:
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PROGRAMMABLE WAKE UP OF MEMORY TRANSFER CONTROLLERS IN A MEMORY TRANSFER ENGINE
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10061544
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Filing Dt:
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02/01/2002
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Title:
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SEMAPHORES WITH INTERRUPT MECHANISM
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10061668
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Filing Dt:
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02/01/2002
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Title:
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MEMORY TRANSFER ENGINE WITH INDEX ADDRESSING SYSTEM
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Patent #:
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Issue Dt:
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05/18/2004
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Application #:
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10062111
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Filing Dt:
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02/01/2002
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Title:
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DIGITAL SYSTEM WITH SPLIT TRANSACTION MEMORY ACCESS
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Patent #:
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Issue Dt:
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06/28/2005
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Application #:
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10062381
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Filing Dt:
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02/01/2002
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Title:
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BUS ANALYZER UNIT WITH PROGRAMMABLE TRACE BUFFERS
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10775461
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Filing Dt:
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02/09/2004
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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METHOD AND SYSTEM FOR PERFORMING PARALLEL INTEGER MULTIPLY ACCUMULATE OPERATIONS ON PACKED DATA
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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10899196
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Filing Dt:
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07/26/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
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Title:
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SYSTEM AND METHOD FOR DMA TRANSFER OF DATA IN SCATTER/GATHER MODE
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Patent #:
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Issue Dt:
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05/11/2010
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Application #:
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11153979
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Filing Dt:
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06/16/2005
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Publication #:
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Pub Dt:
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10/20/2005
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Title:
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METHOD AND SYSTEM FOR PERFORMING PARALLEL INTEGER MULTIPLY ACCUMULATE OPERATIONS ON PACKED DATA
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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12167064
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Filing Dt:
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07/02/2008
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Publication #:
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Pub Dt:
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01/07/2010
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Title:
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SIZE AND RETRY PROGRAMMABLE MULTI-SYNCHRONOUS FIFO
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Patent #:
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Issue Dt:
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04/03/2012
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Application #:
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12167096
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Filing Dt:
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07/02/2008
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Publication #:
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Pub Dt:
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01/07/2010
| | | | |
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Title:
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METHOD AND SYSTEM FOR PERFORMING DMA IN A MULTI-CORE SYSTEM-ON-CHIP USING DEADLINE-BASED SCHEDULING
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Patent #:
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Issue Dt:
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05/29/2012
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Application #:
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12167111
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Filing Dt:
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07/02/2008
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Publication #:
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Pub Dt:
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01/07/2010
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Title:
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METHOD AND SYSTEM FOR DISTRIBUTING A GLOBAL TIMEBASE WITHIN A SYSTEM-ON-CHIP HAVING MULTIPLE CLOCK DOMAINS
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