Total properties:
524
Page
3
of
6
Pages:
1 2 3 4 5 6
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09321298
|
Filing Dt:
|
05/27/1999
|
|
Title:
|
CAVITY DOWN PLASTIC BALL GRID ARRAY MULTI-CHIP MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09322064
|
Filing Dt:
|
05/27/1999
|
|
Title:
|
FLIP CHIP BALL GRID ARRAY PACKAGE WITH LAMINATED SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09329420
|
Filing Dt:
|
06/10/1999
|
|
Title:
|
SELF ALIGNMENT DEVICE FOR BALL GRID ARRAY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09344656
|
Filing Dt:
|
06/25/1999
|
|
Title:
|
PLASTIC PACKAGED OPTOELECTRONIC DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
09345432
|
Filing Dt:
|
07/01/1999
|
|
Title:
|
ROUTING DENSITY ENHANCEMENT FOR SEMICOMDUCTOR BGA PACKAGES AND PRINTED WIRING BOARDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09346100
|
Filing Dt:
|
07/01/1999
|
|
Title:
|
LOW COST BALL GRID ARRAY PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09351220
|
Filing Dt:
|
10/14/1999
|
|
Title:
|
APPARATUS AND METHOD FOR SOLDER ATTACHMENT OF HIGH POWERED TRANSISTORS TO BASE HEATSINK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
09351546
|
Filing Dt:
|
07/12/1999
|
|
Title:
|
METHOD AND APPARATUS FOR CUTTING A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09370856
|
Filing Dt:
|
08/09/1999
|
|
Title:
|
NON-DESTRUCTIVE METHOD OF DETECTING DIE CRACK PROBLEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09375835
|
Filing Dt:
|
08/16/1999
|
|
Title:
|
SEMICONDUCTOR FLIP CHIP BALL GRID ARRAY PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09377887
|
Filing Dt:
|
08/19/1999
|
|
Title:
|
MULTIPLE LAYER TAPE BALL GRID ARRAY PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09385735
|
Filing Dt:
|
08/30/1999
|
|
Title:
|
ETCH STOPS AND ALIGNMENT MARKS FOR BONDED WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09388242
|
Filing Dt:
|
09/01/1999
|
|
Title:
|
DEVICE AND METHOD OF CONTROLLING THE BOWING OF A SOLDERED OR ADHESIVELY BONDED ASSEMBLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
09400767
|
Filing Dt:
|
09/22/1999
|
|
Title:
|
UNIFORM AXIAL LOADING GROUND GLASS JOINT CLAMP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2001
|
Application #:
|
09401690
|
Filing Dt:
|
09/22/1999
|
|
Title:
|
INTEGRATED CIRCUIT PACKAGES WITH IMPROVED EMI CHARACTERISTICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09406308
|
Filing Dt:
|
09/27/1999
|
|
Title:
|
METHOD FOR IMPROVING BALL JOINTS IN SEMICONDUCTOR PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09413605
|
Filing Dt:
|
10/06/1999
|
|
Title:
|
MULTIFUNCTION LEAD FRAME AND INTEGRATED CIRCUIT PACKAGE INCORPORATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09416069
|
Filing Dt:
|
10/12/1999
|
|
Title:
|
ELECTRONIC ASSEMBLY HAVING SHIELDING AND STRAIN-RELIEF MEMBER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
|
09417255
|
Filing Dt:
|
10/12/1999
|
|
Title:
|
METHOD FOR ASSEMBLING TAPE BALL GRID ARRAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09425706
|
Filing Dt:
|
10/22/1999
|
|
Title:
|
LOW PROFILE INTEGRATED CIRCUIT PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09428164
|
Filing Dt:
|
10/27/1999
|
|
Title:
|
SEMICONDUCTOR PACKAGE WITH TRACES ROUTED UNDERNEATH A DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2002
|
Application #:
|
09435971
|
Filing Dt:
|
11/08/1999
|
|
Title:
|
TESTING INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09437559
|
Filing Dt:
|
11/10/1999
|
|
Title:
|
METHOD OF USING BOTH A NON-FILLED FLUX UNDERFILL AND A FILLED FLUX UNDERFILL TO MANUFACTURE A FLIP-CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09440492
|
Filing Dt:
|
11/15/1999
|
|
Title:
|
METHOD OF ADDING FILLER INTO A NON-FILLED UNDERFILL SYSTEM BY USING A HIGHLY FILLED FILLET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09441543
|
Filing Dt:
|
11/16/1999
|
|
Title:
|
BACKSIDE LIQUID CRYSTAL ANALYSIS TECHNIQUE FOR FLIP-CHIP PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2001
|
Application #:
|
09443036
|
Filing Dt:
|
11/18/1999
|
|
Title:
|
DUAL-THICKNESS SOLDER MASK IN INTEGRATED CIRCUIT PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09461609
|
Filing Dt:
|
12/15/1999
|
|
Title:
|
MANUFACTURE OF DIELECTRICALLY ISOLATED INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09464225
|
Filing Dt:
|
12/15/1999
|
|
Title:
|
CORROSION SENSITIVITY STRUCTURES FOR VIAS AND CONTACT HOLES IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09465075
|
Filing Dt:
|
12/16/1999
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2002
| | | | |
|
Title:
|
PROCESS FOR FORMING A DUAL DAMASCENE BOND PAD STRUCTURE OVER ACTIVE CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
09465131
|
Filing Dt:
|
12/16/1999
|
|
Title:
|
METHOD AND APPARATUS FOR THERMAL PROFILING OF FLIP-CHIP PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09465132
|
Filing Dt:
|
12/16/1999
|
|
Title:
|
METHOD AND APPARATUS FOR CLEANING AND REMOVING FLUX FROM AN ELECTRONIC COMPONENT PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09465425
|
Filing Dt:
|
12/20/1999
|
|
Title:
|
METHOD AND STRUCTURE FOR REDUCING THE INCIDENCE OF VOIDING IN AN UNDERFILL LAYER OF AN ELECTRONIC COMPONENT PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09466449
|
Filing Dt:
|
12/17/1999
|
|
Title:
|
ARTICLE COMPRISING OXIDE-BONDABLE SOLDER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09467081
|
Filing Dt:
|
12/10/1999
|
|
Title:
|
PLASTIC BALL GRID ARRAY PACKAGE WITH STRIP LINE CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2004
|
Application #:
|
09467253
|
Filing Dt:
|
12/20/1999
|
|
Title:
|
WIRE BONDING METHOD FOR COPPER INTERCONNECTS IN SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09477306
|
Filing Dt:
|
01/04/2000
|
|
Title:
|
PROGRAMMING A SUBSTRATE FOR ARRAY-TYPE PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2002
|
Application #:
|
09478164
|
Filing Dt:
|
01/05/2000
|
|
Title:
|
SUBSTRATE POSITION LOCATION SYSTEM LSI LOGIC CORPORATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09478972
|
Filing Dt:
|
01/06/2000
|
|
Title:
|
INTERPOSER TAPE FOR SEMICONDUCTOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09488438
|
Filing Dt:
|
01/20/2000
|
|
Title:
|
Loose die fixture
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09489302
|
Filing Dt:
|
01/21/2000
|
|
Title:
|
VERTICALLY INTEGRATED FLIP CHIP SEMICONDUCTOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09492600
|
Filing Dt:
|
01/27/2000
|
|
Title:
|
Die coating material stirring machine
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
|
Application #:
|
09494070
|
Filing Dt:
|
01/28/2000
|
|
Title:
|
HEAT DISSIPATING APPARATUS AND METHOD FOR ELECTRONIC COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2004
|
Application #:
|
09496989
|
Filing Dt:
|
02/02/2000
|
|
Title:
|
HEATSPREADER FOR A FLIP CHIP DEVICE, AND METHOD FOR CONNECTING THE HEATSPREADER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2004
|
Application #:
|
09498005
|
Filing Dt:
|
02/04/2000
|
|
Title:
|
HIGH PERFORMANCE MULTI-CHIP IC PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2002
|
Application #:
|
09499801
|
Filing Dt:
|
02/08/2000
|
|
Title:
|
Interposer for semiconductor package assembly
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09503814
|
Filing Dt:
|
02/15/2000
|
|
Title:
|
Bond pad for a flip chip package, and method of forming the same
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09528882
|
Filing Dt:
|
03/20/2000
|
|
Title:
|
MULTI-CHIP BALL GRID ARRAY IC PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09578082
|
Filing Dt:
|
05/24/2000
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH VARIABLE PIN LOCATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09580522
|
Filing Dt:
|
05/30/2000
|
|
Title:
|
DEVICE AND METHOD FOR PROTECTING ELECTRONIC COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09583126
|
Filing Dt:
|
05/30/2000
|
|
Title:
|
METHODS OF PACKAGING POLARIZATION MAINTAINING FIBERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09596039
|
Filing Dt:
|
06/15/2000
|
|
Title:
|
METHOD FOR ATTACHING SOLDERBALLS BY SELECTIVELY OXIDIZING TRACES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09609582
|
Filing Dt:
|
06/30/2000
|
|
Title:
|
FLIP CHIP SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09612867
|
Filing Dt:
|
07/10/2000
|
|
Title:
|
METHOD OF PLANARIZING DIE SOLDER BALLS BY EMPLOYING A DIE'S WEIGHT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09614854
|
Filing Dt:
|
07/12/2000
|
|
Title:
|
Technique for reducing dambar burrs
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09620939
|
Filing Dt:
|
07/21/2000
|
|
Title:
|
INTEGRATED CIRCUIT PACKAGE HAVING PARTIALLLY EXPOSED CONDUCTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2004
|
Application #:
|
09621110
|
Filing Dt:
|
07/21/2000
|
|
Title:
|
METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
09628067
|
Filing Dt:
|
07/28/2000
|
|
Title:
|
INTEGRATED CIRCUIT PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09631150
|
Filing Dt:
|
08/02/2000
|
|
Title:
|
Vacuum-assisted integrated circuit test socket
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09636498
|
Filing Dt:
|
08/11/2000
|
|
Title:
|
METHOD OF RAPID WAFER BUMPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
09639288
|
Filing Dt:
|
08/15/2000
|
|
Title:
|
INTEGRATED CIRCUIT DIE FOR WIRE BONDING AND FLIP-CHIP MOUNTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09641899
|
Filing Dt:
|
08/18/2000
|
|
Title:
|
INTEGRATED CIRCUIT PACKAGE WITH IMPROVED ESD PROTECTION FOR NO-CONNECT PINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09642216
|
Filing Dt:
|
08/18/2000
|
|
Title:
|
Oxide-bondable solder
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09651308
|
Filing Dt:
|
08/30/2000
|
|
Title:
|
THIN FORM FACTOR FLIP CHIP BALL GRID ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09669278
|
Filing Dt:
|
09/26/2000
|
|
Title:
|
DUAL IN-LINE BGA BALL MOUNTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
09680759
|
Filing Dt:
|
10/06/2000
|
|
Title:
|
BALANCED COEFFICIENT OF THERMAL EXPANSION FOR FLIP CHIP BALL GRID ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
09687263
|
Filing Dt:
|
10/12/2000
|
|
Title:
|
INSULATED BONDING WIRE FOR MICROELECTRONIC PACKAGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09695540
|
Filing Dt:
|
10/24/2000
|
|
Title:
|
APPARATUS SUITABLE FOR MOUNTING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2004
|
Application #:
|
09698175
|
Filing Dt:
|
10/30/2000
|
|
Title:
|
METHOD OF MANUFACTURING AND MOUNTING ELECTRONIC DEVICES TO LIMIT THE EFFECTS OF PARASITICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
09731596
|
Filing Dt:
|
12/06/2000
|
|
Title:
|
METHOD FOR PROBING A SEMICONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
09735085
|
Filing Dt:
|
12/11/2000
|
|
Title:
|
INTERCONNECTOR AND METHOD OF CONNECTING PROBES TO A DIE FOR FUNCTIONAL ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
09752626
|
Filing Dt:
|
12/28/2000
|
|
Title:
|
SIX-TO-ONE SIGNAL/POWER RATIO BUMP AND TRACE PATTERN FOR FLIP CHIP DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2002
|
Application #:
|
09753000
|
Filing Dt:
|
12/30/2000
|
|
Title:
|
IRREGULAR GRID BOND PAD LAYOUT ARRANGEMENT FOR A FLIP CHIP PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09766104
|
Filing Dt:
|
01/19/2001
|
|
Title:
|
HEAT SINK WITH CHIP DIE EMC GROUND INTERCONNECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09781423
|
Filing Dt:
|
02/13/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/15/2002
| | | | |
|
Title:
|
LEAD STRUCTURE FOR SEALING PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09801007
|
Filing Dt:
|
03/07/2001
|
|
Title:
|
METHOD FOR MANUFACTURING A DUAL CHIP IN PACKAGE WITH A FLIP CHIP DIE MOUNTED ON A WIRE BONDED DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09802424
|
Filing Dt:
|
03/09/2001
|
|
Title:
|
SUBSTRATE PROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09839925
|
Filing Dt:
|
04/20/2001
|
|
Title:
|
CONTACT ESCAPE PATTERN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09843443
|
Filing Dt:
|
04/26/2001
|
|
Title:
|
DUAL CHIP IN PACKAGE WITH A WIRE BONDED DIE MOUNTED TO A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09846435
|
Filing Dt:
|
05/01/2001
|
|
Title:
|
TEST FIXTURE FOR FLIP CHIP BALL GRID ARRAY CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09864577
|
Filing Dt:
|
05/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2001
| | | | |
|
Title:
|
WIRE BONDING TO COPPER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09873551
|
Filing Dt:
|
06/04/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2001
| | | | |
|
Title:
|
CIRCUIT AND METHOD FOR PROVIDING INTERCONNECTIONS AMONG INDIVIDUAL INTEGRATED CIRCUIT CHIPS IN A MULTI-CHIP MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
09876522
|
Filing Dt:
|
06/07/2001
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2002
| | | | |
|
Title:
|
PRINTED WIRING BOARD HAVING A DISCONTINUOUS PLATING LAYER AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09884711
|
Filing Dt:
|
06/18/2001
|
|
Title:
|
UNIVERSAL TEST COUPON FOR PERFORMING PREQUALIFICATION TESTS ON SUBSTRATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09885299
|
Filing Dt:
|
06/20/2001
|
|
Title:
|
HIGH DENSITY SIGNAL ROUTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09885491
|
Filing Dt:
|
06/20/2001
|
|
Title:
|
SPLITTING AND ASSIGNING POWER PLANES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
09885687
|
Filing Dt:
|
06/19/2001
|
|
Title:
|
SEMICONDUCTOR DEVICE PACKAGE SUBSTRATE PROBE FIXTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2003
|
Application #:
|
09894210
|
Filing Dt:
|
06/27/2001
|
|
Title:
|
MICROSTRIP PACKAGE HAVING OPTIMIZED SIGNAL LINE IMPEDANCE CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
09921028
|
Filing Dt:
|
08/02/2001
|
|
Title:
|
APPARATUS AND METHOD OF PROTECTING A PROBE CARD DURING A SORT SEQUENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09928071
|
Filing Dt:
|
08/10/2001
|
|
Title:
|
INTEGRATED CIRCUIT TEST VEHICLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
09932307
|
Filing Dt:
|
08/17/2001
|
|
Title:
|
ADHESIVE PAD HAVING EMC SHIELDING CHARACTERISTICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
09932716
|
Filing Dt:
|
08/17/2001
|
|
Title:
|
CHARACTERISTIC IMPEDANCE EQUALIZER AND AN INTEGRATED CIRCUIT PACKAGE EMPLOYING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
|
09940130
|
Filing Dt:
|
08/27/2001
|
|
Title:
|
OVERMOLD INTEGRATED CIRCUIT PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
09946033
|
Filing Dt:
|
09/04/2001
|
|
Title:
|
INTEGRATED CIRCUIT HAVING DEDICATED PROBE PADS FOR USE IN TESTING DENSELY PATTERNED BONDING PADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
09949207
|
Filing Dt:
|
09/07/2001
|
|
Title:
|
BONDING PAD INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09967195
|
Filing Dt:
|
09/28/2001
|
|
Title:
|
TRANSMISSION EQUALIZATION SYSTEM AND AN INTEGRATED CIRCUIT PACKAGE EMPLOYING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2003
|
Application #:
|
09968286
|
Filing Dt:
|
10/01/2001
|
|
Title:
|
DIE POWER DISTRIBUTION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
09974157
|
Filing Dt:
|
10/09/2001
|
|
Title:
|
INTERPOSER FOR SEMICONDUCTOR PACKAGE ASSEMBLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09975871
|
Filing Dt:
|
10/12/2001
|
|
Title:
|
INTEGRATED CIRCUIT PACKAGE VIA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09993466
|
Filing Dt:
|
11/05/2001
|
|
Title:
|
CHIP-OVER-CHIP INTEGRATED CIRCUIT PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
09994567
|
Filing Dt:
|
11/27/2001
|
|
Title:
|
HIGH DENSITY INPUT OUTPUT
|
|
