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Reel/Frame:054452/0776   Pages: 53
Recorded: 11/17/2020
Attorney Dkt #:0941-4477M
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 28
1
Patent #:
Issue Dt:
04/22/2014
Application #:
13564071
Filing Dt:
08/01/2012
Publication #:
Pub Dt:
08/08/2013
Title:
METHODS FOR PFET FABRICATION USING APM SOLUTIONS
2
Patent #:
Issue Dt:
04/16/2019
Application #:
15444899
Filing Dt:
02/28/2017
Publication #:
Pub Dt:
08/30/2018
Title:
METHODOLOGY FOR MODEL-BASED SELF-ALIGNED VIA AWARENESS IN OPTICAL PROXIMITY CORRECTION
3
Patent #:
Issue Dt:
02/26/2019
Application #:
15456757
Filing Dt:
03/13/2017
Publication #:
Pub Dt:
09/13/2018
Title:
SUBSTANTIALLY DEFECT-FREE POLYSILICON GATE ARRAYS
4
Patent #:
Issue Dt:
02/05/2019
Application #:
15478377
Filing Dt:
04/04/2017
Publication #:
Pub Dt:
10/04/2018
Title:
SRAF INSERTION WITH ARTIFICIAL NEURAL NETWORK
5
Patent #:
Issue Dt:
09/03/2019
Application #:
15588984
Filing Dt:
05/08/2017
Publication #:
Pub Dt:
11/08/2018
Title:
PREDICTION OF PROCESS-SENSITIVE GEOMETRIES WITH MACHINE LEARNING
6
Patent #:
Issue Dt:
04/16/2019
Application #:
15597202
Filing Dt:
05/17/2017
Publication #:
Pub Dt:
11/22/2018
Title:
PROBE CARD SUPPORT INSERT, CONTAINER, SYSTEM AND METHOD FOR STORING AND TRANSPORTING ONE OR MORE PROBE CARDS
7
Patent #:
Issue Dt:
06/25/2019
Application #:
15597277
Filing Dt:
05/17/2017
Publication #:
Pub Dt:
11/22/2018
Title:
DUMMY ASSIST FEATURES FOR PATTERN SUPPORT
8
Patent #:
Issue Dt:
04/02/2019
Application #:
15602810
Filing Dt:
05/23/2017
Publication #:
Pub Dt:
11/29/2018
Title:
MULTI-STAGE PATTERN RECOGNITION IN CIRCUIT DESIGNS
9
Patent #:
Issue Dt:
10/01/2019
Application #:
15609621
Filing Dt:
05/31/2017
Publication #:
Pub Dt:
12/06/2018
Title:
SHIELDED SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING SHIELDED SEMICONDUCTOR DEVICES
10
Patent #:
Issue Dt:
03/19/2019
Application #:
15617403
Filing Dt:
06/08/2017
Publication #:
Pub Dt:
12/13/2018
Title:
MATCHING IC DESIGN PATTERNS USING WEIGHTED XOR DENSITY
11
Patent #:
Issue Dt:
06/18/2019
Application #:
15622061
Filing Dt:
06/13/2017
Publication #:
Pub Dt:
12/13/2018
Title:
METHODS, APPARATUS AND SYSTEM FOR THRESHOLD VOLTAGE CONTROL IN FINFET DEVICES
12
Patent #:
Issue Dt:
07/16/2019
Application #:
15624764
Filing Dt:
06/16/2017
Publication #:
Pub Dt:
12/20/2018
Title:
MODELING 3D PHYSICAL CONNECTIVITY INTO PLANAR 2D DOMAIN TO IDENTIFY VIA REDUNDANCY
13
Patent #:
Issue Dt:
05/21/2019
Application #:
15652594
Filing Dt:
07/18/2017
Publication #:
Pub Dt:
01/24/2019
Title:
INTERCONNECT STRUCTURES FOR A SECURITY APPLICATION
14
Patent #:
Issue Dt:
02/05/2019
Application #:
15653638
Filing Dt:
07/19/2017
Publication #:
Pub Dt:
01/24/2019
Title:
VIA AND SKIP VIA STRUCTURES
15
Patent #:
Issue Dt:
08/06/2019
Application #:
15662419
Filing Dt:
07/28/2017
Publication #:
Pub Dt:
01/31/2019
Title:
IC LAYOUT POST-DECOMPOSITION MASK ALLOCATION OPTIMIZATION
16
Patent #:
Issue Dt:
04/30/2019
Application #:
15665974
Filing Dt:
08/01/2017
Publication #:
Pub Dt:
02/07/2019
Title:
SPLIT PROBE PAD STRUCTURE AND METHOD
17
Patent #:
Issue Dt:
06/04/2019
Application #:
15670158
Filing Dt:
08/07/2017
Publication #:
Pub Dt:
02/07/2019
Title:
ALIGNMENT KEY DESIGN RULE CHECK FOR CORRECT PLACEMENT OF ABUTTING CELLS IN AN INTEGRATED CIRCUIT
18
Patent #:
Issue Dt:
02/05/2019
Application #:
15693651
Filing Dt:
09/01/2017
Title:
SELF-ALIGNED METAL WIRE ON CONTACT STRUCTURE AND METHOD FOR FORMING SAME
19
Patent #:
Issue Dt:
04/30/2019
Application #:
15709730
Filing Dt:
09/20/2017
Publication #:
Pub Dt:
03/21/2019
Title:
METHODS FOR FORMING FINS
20
Patent #:
Issue Dt:
09/03/2019
Application #:
15719680
Filing Dt:
09/29/2017
Publication #:
Pub Dt:
04/04/2019
Title:
GENERATING RISK INVENTORY AND COMMON PROCESS WINDOW FOR ADJUSTMENT OF MANUFACTURING TOOL
21
Patent #:
Issue Dt:
08/20/2019
Application #:
15720182
Filing Dt:
09/29/2017
Publication #:
Pub Dt:
04/04/2019
Title:
GEOMETRY VECTORIZATION FOR MASK PROCESS CORRECTION
22
Patent #:
Issue Dt:
08/20/2019
Application #:
15730830
Filing Dt:
10/12/2017
Publication #:
Pub Dt:
04/18/2019
Title:
METHODOLOGY FOR POST-INTEGRATION AWARENESS IN OPTICAL PROXIMITY CORRECTION
23
Patent #:
Issue Dt:
09/03/2019
Application #:
15805179
Filing Dt:
11/07/2017
Publication #:
Pub Dt:
05/09/2019
Title:
PELLICLE REPLACEMENT IN EUV MASK FLOW
24
Patent #:
Issue Dt:
08/06/2019
Application #:
15829459
Filing Dt:
12/01/2017
Publication #:
Pub Dt:
06/06/2019
Title:
LOGIC LAYOUT WITH REDUCED AREA AND METHOD OF MAKING THE SAME
25
Patent #:
Issue Dt:
03/12/2019
Application #:
15860231
Filing Dt:
01/02/2018
Title:
CUT-FIRST APPROACH WITH SELF-ALIGNMENT DURING LINE PATTERNING
26
Patent #:
Issue Dt:
01/29/2019
Application #:
15913547
Filing Dt:
03/06/2018
Title:
SEMICONDUCTOR DEVICES WITH ROBUST LOW-K SIDEWALL SPACERS AND METHOD FOR PRODUCING THE SAME
27
Patent #:
Issue Dt:
06/18/2019
Application #:
16159877
Filing Dt:
10/15/2018
Title:
FinFET CUT ISOLATION OPENING REVISION TO COMPENSATE FOR OVERLAY INACCURACY
28
Patent #:
Issue Dt:
09/24/2019
Application #:
16398841
Filing Dt:
04/30/2019
Title:
FinFET CUT ISOLATION OPENING REVISION TO COMPENSATE FOR OVERLAY INACCURACY
Assignor
1
Exec Dt:
05/15/2020
Assignee
1
NO. 8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK
HSINCHU, TAIWAN 300-78
Correspondence name and address
BIRCH, STEWART, KOLASCH & BIRCH, LLP
8110 GATEHOUSE ROAD, SUITE 100 EAST
FALLS CHURCH, VA 22042-1248

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