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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:037254/0782   Pages: 13
Recorded: 12/09/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 210
Page 1 of 3
Pages: 1 2 3
1
Patent #:
7838921
Issue Dt:
11/23/2010
Application #:
11526149
Filing Dt:
09/22/2006
Publication #:
US20080073694
Pub Dt:
03/27/2008
Title:
MEMORY CELL ARRANGEMENTS
2
Patent #:
7783826
Issue Dt:
08/24/2010
Application #:
11529711
Filing Dt:
09/28/2006
Publication #:
US20080082762
Pub Dt:
04/03/2008
Title:
DATA BUS WIDTH CONVERTER
3
Patent #:
7802166
Issue Dt:
09/21/2010
Application #:
11535961
Filing Dt:
09/27/2006
Publication #:
US20080126843
Pub Dt:
05/29/2008
Title:
MEMORY CONTROLLER, MEMORY CIRCUIT AND MEMORY SYSTEM WITH A MEMORY CONTROLLER AND A MEMORY CIRCUIT
4
Patent #:
7836386
Issue Dt:
11/16/2010
Application #:
11535968
Filing Dt:
09/27/2006
Publication #:
US20080075156
Pub Dt:
03/27/2008
Title:
PHASE SHIFT ADJUSTING METHOD AND CIRCUIT
5
Patent #:
7844888
Issue Dt:
11/30/2010
Application #:
11537401
Filing Dt:
09/29/2006
Publication #:
US20080082898
Pub Dt:
04/03/2008
Title:
ELECTRONIC DEVICE, METHOD FOR OPERATING AN ELECTRONIC DEVICE, MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT
6
Patent #:
7865641
Issue Dt:
01/04/2011
Application #:
11540009
Filing Dt:
09/29/2006
Publication #:
US20080080564
Pub Dt:
04/03/2008
Title:
SYNCHRONIZATION AND SCHEDULING OF A DUAL MASTER SERIAL CHANNEL
7
Patent #:
7551476
Issue Dt:
06/23/2009
Application #:
11541973
Filing Dt:
10/02/2006
Publication #:
US20080080228
Pub Dt:
04/03/2008
Title:
RESISTIVE MEMORY HAVING SHUNTED MEMORY CELLS
8
Patent #:
7405992
Issue Dt:
07/29/2008
Application #:
11552752
Filing Dt:
10/25/2006
Publication #:
US20080106967
Pub Dt:
05/08/2008
Title:
METHOD AND APPARATUS FOR COMMUNICATING COMMAND AND ADDRESS SIGNALS
9
Patent #:
7587571
Issue Dt:
09/08/2009
Application #:
11564764
Filing Dt:
11/29/2006
Publication #:
US20080123438
Pub Dt:
05/29/2008
Title:
EVALUATION UNIT IN AN INTEGRATED CIRCUIT
10
Patent #:
7385872
Issue Dt:
06/10/2008
Application #:
11581350
Filing Dt:
10/17/2006
Publication #:
US20080089164
Pub Dt:
04/17/2008
Title:
METHOD AND APPARATUS FOR INCREASING CLOCK FREQUENCY AND DATA RATE FOR SEMICONDUCTOR DEVICES
11
Patent #:
7879395
Issue Dt:
02/01/2011
Application #:
11582239
Filing Dt:
10/17/2006
Publication #:
US20080090101
Pub Dt:
04/17/2008
Title:
METHOD OF PREPARING A COATING SOLUTION AND A CORRESPONDING USE OF THE COATING SOLUTION FOR COATING A SUBSTRATE
12
Patent #:
7772126
Issue Dt:
08/10/2010
Application #:
11583145
Filing Dt:
10/19/2006
Publication #:
US20080093710
Pub Dt:
04/24/2008
Title:
HARD MASK ARRANGEMENT, CONTACT ARRANGEMENT AND METHODS OF PATTERNING A SUBSTRATE AND MANUFACTURING A CONTACT ARRANGEMENT
13
Patent #:
7405993
Issue Dt:
07/29/2008
Application #:
11589984
Filing Dt:
10/31/2006
Publication #:
US20080080292
Pub Dt:
04/03/2008
Title:
CONTROL COMPONENT FOR CONTROLLING A SEMICONDUCTOR MEMORY COMPONENT IN A SEMICONDUCTOR MEMORY MODULE
14
Patent #:
7577053
Issue Dt:
08/18/2009
Application #:
11598403
Filing Dt:
11/13/2006
Publication #:
US20080112250
Pub Dt:
05/15/2008
Title:
MEMORY INCLUDING DEEP POWER DOWN MODE
15
Patent #:
8201071
Issue Dt:
06/12/2012
Application #:
11599992
Filing Dt:
11/15/2006
Publication #:
US20080115030
Pub Dt:
05/15/2008
Title:
INFORMATION TRANSMISSION AND RECEPTION
16
Patent #:
7679980
Issue Dt:
03/16/2010
Application #:
11602719
Filing Dt:
11/21/2006
Publication #:
US20080117704
Pub Dt:
05/22/2008
Title:
RESISTIVE MEMORY INCLUDING SELECTIVE REFRESH OPERATION
17
Patent #:
7436695
Issue Dt:
10/14/2008
Application #:
11602720
Filing Dt:
11/21/2006
Publication #:
US20080117667
Pub Dt:
05/22/2008
Title:
RESISTIVE MEMORY INCLUDING BIPOLAR TRANSISTOR ACCESS DEVICES
18
Patent #:
7539050
Issue Dt:
05/26/2009
Application #:
11603636
Filing Dt:
11/22/2006
Publication #:
US20080117663
Pub Dt:
05/22/2008
Title:
RESISTIVE MEMORY INCLUDING REFRESH OPERATION
19
Patent #:
7721130
Issue Dt:
05/18/2010
Application #:
11604666
Filing Dt:
11/27/2006
Publication #:
US20080126816
Pub Dt:
05/29/2008
Title:
APPARATUS AND METHOD FOR SWITCHING AN APPARATUS TO A POWER SAVING MODE
20
Patent #:
7619917
Issue Dt:
11/17/2009
Application #:
11605079
Filing Dt:
11/28/2006
Publication #:
US20080123398
Pub Dt:
05/29/2008
Title:
MEMORY CELL WITH TRIGGER ELEMENT
21
Patent #:
7611972
Issue Dt:
11/03/2009
Application #:
11606812
Filing Dt:
11/29/2006
Publication #:
US20080121963
Pub Dt:
05/29/2008
Title:
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
22
Patent #:
7639066
Issue Dt:
12/29/2009
Application #:
11611222
Filing Dt:
12/15/2006
Publication #:
US20080142854
Pub Dt:
06/19/2008
Title:
CIRCUIT AND METHOD FOR SUPPRESSING GATE INDUCED DRAIN LEAKAGE
23
Patent #:
7663955
Issue Dt:
02/16/2010
Application #:
11615101
Filing Dt:
12/22/2006
Publication #:
US20080151663
Pub Dt:
06/26/2008
Title:
DELAYED SENSE AMPLIFIER MULTIPLEXER ISOLATION
24
Patent #:
7443751
Issue Dt:
10/28/2008
Application #:
11615118
Filing Dt:
12/22/2006
Publication #:
US20080151647
Pub Dt:
06/26/2008
Title:
PROGRAMMABLE SENSE AMPLIFIER MULTIPLEXER CIRCUIT WITH DYNAMIC LATCHING MODE
25
Patent #:
7738570
Issue Dt:
06/15/2010
Application #:
11615418
Filing Dt:
12/22/2006
Publication #:
US20080152026
Pub Dt:
06/26/2008
Title:
SENDER, RECEIVER AND METHOD OF TRANSFERRING INFORMATION FROM A SENDER TO A RECEIVER
26
Patent #:
7873857
Issue Dt:
01/18/2011
Application #:
11624465
Filing Dt:
01/18/2007
Publication #:
US20080177911
Pub Dt:
07/24/2008
Title:
MULTI-COMPONENT MODULE FLY-BY OUTPUT ALIGNMENT ARRANGEMENT AND METHOD
27
Patent #:
7692949
Issue Dt:
04/06/2010
Application #:
11633210
Filing Dt:
12/04/2006
Publication #:
US20080130351
Pub Dt:
06/05/2008
Title:
MULTI-BIT RESISTIVE MEMORY
28
Patent #:
7525357
Issue Dt:
04/28/2009
Application #:
11638324
Filing Dt:
12/13/2006
Publication #:
US20080143427
Pub Dt:
06/19/2008
Title:
CIRCUIT AND METHOD FOR ADJUSTING A VOLTAGE DROP
29
Patent #:
7917825
Issue Dt:
03/29/2011
Application #:
11639161
Filing Dt:
12/15/2006
Publication #:
US20080148007
Pub Dt:
06/19/2008
Title:
METHOD AND APPARATUS FOR SELECTIVELY UTILIZING INFORMATION WITHIN A SEMICONDUCTOR DEVICE
30
Patent #:
7405591
Issue Dt:
07/29/2008
Application #:
11641545
Filing Dt:
12/19/2006
Publication #:
US20080143386
Pub Dt:
06/19/2008
Title:
CONCEPT FOR INTERFACING A FIRST CIRCUIT REQUIRING A FIRST SUPPLY VOLTAGE AND A SECOND SUPPLY CIRCUIT REQUIRING A SECOND SUPPLY VOLTAGE
31
Patent #:
7564114
Issue Dt:
07/21/2009
Application #:
11644090
Filing Dt:
12/21/2006
Publication #:
US20080149980
Pub Dt:
06/26/2008
Title:
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
32
Patent #:
7936201
Issue Dt:
05/03/2011
Application #:
11644998
Filing Dt:
12/22/2006
Publication #:
US20080155150
Pub Dt:
06/26/2008
Title:
APPARATUS AND METHOD FOR PROVIDING A SIGNAL FOR TRANSMISSION VIA A SIGNAL LINE
33
Patent #:
7795096
Issue Dt:
09/14/2010
Application #:
11647602
Filing Dt:
12/29/2006
Publication #:
US20080157211
Pub Dt:
07/03/2008
Title:
METHOD OF FORMING AN INTEGRATED CIRCUIT WITH TWO TYPES OF TRANSISTORS
34
Patent #:
7797511
Issue Dt:
09/14/2010
Application #:
11650120
Filing Dt:
01/05/2007
Publication #:
US20080168217
Pub Dt:
07/10/2008
Title:
MEMORY REFRESH SYSTEM AND METHOD
35
Patent #:
7727837
Issue Dt:
06/01/2010
Application #:
11669613
Filing Dt:
01/31/2007
Publication #:
US20080182378
Pub Dt:
07/31/2008
Title:
METHOD OF PRODUCING AN INTEGRATED CIRCUIT HAVING A CAPACITOR WITH A SUPPORTING LAYER
36
Patent #:
7842977
Issue Dt:
11/30/2010
Application #:
11675460
Filing Dt:
02/15/2007
Publication #:
US20080197428
Pub Dt:
08/21/2008
Title:
GATE ELECTRODE STRUCTURE, MOS FIELD EFFECT TRANSISTORS AND METHODS OF MANUFACTURING THE SAME
37
Patent #:
7462038
Issue Dt:
12/09/2008
Application #:
11676622
Filing Dt:
02/20/2007
Publication #:
US20080200046
Pub Dt:
08/21/2008
Title:
INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME
38
Patent #:
7867912
Issue Dt:
01/11/2011
Application #:
11676635
Filing Dt:
02/20/2007
Publication #:
US20080197394
Pub Dt:
08/21/2008
Title:
METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES
39
Patent #:
7840876
Issue Dt:
11/23/2010
Application #:
11676774
Filing Dt:
02/20/2007
Publication #:
US20080201626
Pub Dt:
08/21/2008
Title:
POWER SAVINGS FOR MEMORY WITH ERROR CORRECTION MODE
40
Patent #:
7763987
Issue Dt:
07/27/2010
Application #:
11679295
Filing Dt:
02/27/2007
Publication #:
US20080203586
Pub Dt:
08/28/2008
Title:
INTEGRATED CIRCUIT AND METHODS OF MANUFACTURING A CONTACT ARRANGEMENT AND AN INTERCONNECTION ARRANGEMENT
41
Patent #:
7617354
Issue Dt:
11/10/2009
Application #:
11683629
Filing Dt:
03/08/2007
Publication #:
US20080219074
Pub Dt:
09/11/2008
Title:
ABBREVIATED BURST DATA TRANSFERS FOR SEMICONDUCTOR MEMORY
42
Patent #:
7765418
Issue Dt:
07/27/2010
Application #:
11686450
Filing Dt:
03/15/2007
Publication #:
US20080231242
Pub Dt:
09/25/2008
Title:
MULTI-MODE VOLTAGE SUPPLY CIRCUIT
43
Patent #:
7849349
Issue Dt:
12/07/2010
Application #:
11692245
Filing Dt:
03/28/2007
Publication #:
US20080238483
Pub Dt:
10/02/2008
Title:
REDUCED-DELAY CLOCKED LOGIC
44
Patent #:
7638869
Issue Dt:
12/29/2009
Application #:
11692637
Filing Dt:
03/28/2007
Publication #:
US20080237891
Pub Dt:
10/02/2008
Title:
SEMICONDUCTOR DEVICE
45
Patent #:
7656697
Issue Dt:
02/02/2010
Application #:
11693391
Filing Dt:
03/29/2007
Publication #:
US20080239788
Pub Dt:
10/02/2008
Title:
INTEGRATED CIRCUIT HAVING A RESISTIVELY SWITCHING MEMORY AND METHOD
46
Patent #:
7539039
Issue Dt:
05/26/2009
Application #:
11694393
Filing Dt:
03/30/2007
Publication #:
US20080205118
Pub Dt:
08/28/2008
Title:
INTEGRATED CIRCUIT HAVING A RESISTIVE SWITCHING DEVICE
47
Patent #:
7679984
Issue Dt:
03/16/2010
Application #:
11695676
Filing Dt:
04/03/2007
Publication #:
US20080247259
Pub Dt:
10/09/2008
Title:
CONFIGURABLE MEMORY DATA PATH
48
Patent #:
7760569
Issue Dt:
07/20/2010
Application #:
11696777
Filing Dt:
04/05/2007
Publication #:
US20080247252
Pub Dt:
10/09/2008
Title:
SEMICONDUCTOR MEMORY DEVICE WITH TEMPERATURE CONTROL
49
Patent #:
7984355
Issue Dt:
07/19/2011
Application #:
11697792
Filing Dt:
04/09/2007
Publication #:
US20080250292
Pub Dt:
10/09/2008
Title:
MEMORY MODULE WITH RANKS OF MEMORY CHIPS
50
Patent #:
7554875
Issue Dt:
06/30/2009
Application #:
11700399
Filing Dt:
01/31/2007
Publication #:
US20080181044
Pub Dt:
07/31/2008
Title:
BUS STRUCTURE, MEMORY CHIP AND INTEGRATED CIRCUIT
51
Patent #:
7539034
Issue Dt:
05/26/2009
Application #:
11701006
Filing Dt:
02/01/2007
Publication #:
US20080189480
Pub Dt:
08/07/2008
Title:
MEMORY CONFIGURED ON A COMMON SUBSTRATE
52
Patent #:
7800093
Issue Dt:
09/21/2010
Application #:
11701198
Filing Dt:
02/01/2007
Publication #:
US20080185571
Pub Dt:
08/07/2008
Title:
RESISTIVE MEMORY INCLUDING BURIED WORD LINES
53
Patent #:
7605037
Issue Dt:
10/20/2009
Application #:
11704783
Filing Dt:
02/09/2007
Publication #:
US20080192526
Pub Dt:
08/14/2008
Title:
MANUFACTURING METHOD FOR AN INTEGRATED SEMICONDUCTOR MEMORY DEVICE AND CORRESPONDING SEMICONDUCTOR MEMORY DEVICE
54
Patent #:
7898847
Issue Dt:
03/01/2011
Application #:
11715749
Filing Dt:
03/08/2007
Publication #:
US20080219040
Pub Dt:
09/11/2008
Title:
METHOD TO PREVENT OVERRESET
55
Patent #:
7728405
Issue Dt:
06/01/2010
Application #:
11715824
Filing Dt:
03/08/2007
Publication #:
US20080217732
Pub Dt:
09/11/2008
Title:
CARBON MEMORY
56
Patent #:
8207976
Issue Dt:
06/26/2012
Application #:
11726401
Filing Dt:
03/21/2007
Publication #:
US20080225603
Pub Dt:
09/18/2008
Title:
CIRCUIT
57
Patent #:
7723771
Issue Dt:
05/25/2010
Application #:
11731457
Filing Dt:
03/30/2007
Publication #:
US20080237791
Pub Dt:
10/02/2008
Title:
ZIRCONIUM OXIDE BASED CAPACITOR AND PROCESS TO MANUFACTURE THE SAME
58
Patent #:
7688660
Issue Dt:
03/30/2010
Application #:
11734433
Filing Dt:
04/12/2007
Publication #:
US20080253179
Pub Dt:
10/16/2008
Title:
SEMICONDUCTOR DEVICE, AN ELECTRONIC DEVICE AND A METHOD FOR OPERATING THE SAME
59
Patent #:
7642572
Issue Dt:
01/05/2010
Application #:
11735164
Filing Dt:
04/13/2007
Publication #:
US20080253160
Pub Dt:
10/16/2008
Title:
INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT
60
Patent #:
7514973
Issue Dt:
04/07/2009
Application #:
11735748
Filing Dt:
04/16/2007
Publication #:
US20080252346
Pub Dt:
10/16/2008
Title:
CIRCUIT HAVING A CLOCK SIGNAL SYNCHRONIZING DEVICE WITH CAPABILITY TO FILTER CLOCK-JITTER
61
Patent #:
8779495
Issue Dt:
07/15/2014
Application #:
11737531
Filing Dt:
04/19/2007
Publication #:
US20080258203
Pub Dt:
10/23/2008
Title:
STACKED SONOS MEMORY
62
Patent #:
8018070
Issue Dt:
09/13/2011
Application #:
11738086
Filing Dt:
04/20/2007
Publication #:
US20080261395
Pub Dt:
10/23/2008
Title:
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES AND MASK SYSTEMS USED IN THE MANUFACTURING OF SEMICONDUCTOR DEVICES
63
Patent #:
7719886
Issue Dt:
05/18/2010
Application #:
11743987
Filing Dt:
05/03/2007
Publication #:
US20080273378
Pub Dt:
11/06/2008
Title:
MULTI-LEVEL RESISTIVE MEMORY CELL USING DIFFERENT CRYSTALLIZATION SPEEDS
64
Patent #:
7577023
Issue Dt:
08/18/2009
Application #:
11744487
Filing Dt:
05/04/2007
Publication #:
US20080273371
Pub Dt:
11/06/2008
Title:
MEMORY INCLUDING WRITE CIRCUIT FOR PROVIDING MULTIPLE RESET PULSES
65
Patent #:
7440347
Issue Dt:
10/21/2008
Application #:
11744790
Filing Dt:
05/04/2007
Publication #:
US20080273407
Pub Dt:
11/06/2008
Title:
CIRCUIT AND METHOD TO FIND WORDLINE-BITLINE SHORTS IN A DRAM
66
Patent #:
8158485
Issue Dt:
04/17/2012
Application #:
11744962
Filing Dt:
05/07/2007
Publication #:
US20080277760
Pub Dt:
11/13/2008
Title:
INTEGRATED CIRCUIT DEVICE HAVING OPENINGS IN A LAYERED STRUCTURE
67
Patent #:
7956644
Issue Dt:
06/07/2011
Application #:
11746946
Filing Dt:
05/10/2007
Publication #:
US20080282001
Pub Dt:
11/13/2008
Title:
PEAK POWER REDUCTION USING FIXED BIT INVERSION
68
Patent #:
7794614
Issue Dt:
09/14/2010
Application #:
11754813
Filing Dt:
05/29/2007
Publication #:
US20080296737
Pub Dt:
12/04/2008
Title:
METHODS FOR GENERATING SUBLITHOGRAPHIC STRUCTURES.
69
Patent #:
7773232
Issue Dt:
08/10/2010
Application #:
11755063
Filing Dt:
05/30/2007
Publication #:
US20080297765
Pub Dt:
12/04/2008
Title:
APPARATUS AND METHOD FOR DETERMINING TRENCH PARAMETERS
70
Patent #:
7697354
Issue Dt:
04/13/2010
Application #:
11755101
Filing Dt:
05/30/2007
Publication #:
US20080298149
Pub Dt:
12/04/2008
Title:
INTEGRATED CIRCUIT MEMORY DEVICE RESPONSIVE TO WORD LINE/BIT LINE SHORT-CIRCUIT
71
Patent #:
8040710
Issue Dt:
10/18/2011
Application #:
11756541
Filing Dt:
05/31/2007
Publication #:
US20080301349
Pub Dt:
12/04/2008
Title:
SEMICONDUCTOR MEMORY ARRANGEMENT
72
Patent #:
7671353
Issue Dt:
03/02/2010
Application #:
11757712
Filing Dt:
06/04/2007
Publication #:
US20080296553
Pub Dt:
12/04/2008
Title:
INTEGRATED CIRCUIT HAVING CONTACT INCLUDING MATERIAL BETWEEN SIDEWALLS
73
Patent #:
7545019
Issue Dt:
06/09/2009
Application #:
11759528
Filing Dt:
06/07/2007
Publication #:
US20080304311
Pub Dt:
12/11/2008
Title:
INTEGRATED CIRCUIT INCLUDING LOGIC PORTION AND MEMORY PORTION
74
Patent #:
7671354
Issue Dt:
03/02/2010
Application #:
11760913
Filing Dt:
06/11/2007
Publication #:
US20080303013
Pub Dt:
12/11/2008
Title:
INTEGRATED CIRCUIT INCLUDING SPACER DEFINED ELECTRODE
75
Patent #:
7975170
Issue Dt:
07/05/2011
Application #:
11763593
Filing Dt:
06/15/2007
Publication #:
US20080313494
Pub Dt:
12/18/2008
Title:
MEMORY REFRESH SYSTEM AND METHOD
76
Patent #:
7636156
Issue Dt:
12/22/2009
Application #:
11763837
Filing Dt:
06/15/2007
Publication #:
US20080309927
Pub Dt:
12/18/2008
Title:
WAFER INSPECTION SYSTEM AND METHOD
77
Patent #:
7745812
Issue Dt:
06/29/2010
Application #:
11766231
Filing Dt:
06/21/2007
Publication #:
US20080315172
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Assignor
1
INFINEON TECHNOLOGIES AG
Exec Dt:
07/08/2015
Assignee
1
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE
DUBLIN 2, IRELAND
Correspondence name and address
POLARIS INNOVATIONS LIMITED
303 TERRY FOX DRIVE
SUITE 300
OTTAWA, K2K 3J1 CANADA

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