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Reel/Frame:	037876/0790			Pages:	12
		Recorded:	02/22/2016
Attorney Dkt #:	AMD ASSIGNMENT SUBMISSION
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 48

Patent #:	5937302	Issue Dt:	08/10/1999	Application #:	08781092	Filing Dt:	01/08/1997
Title:	METHOD OF FORMING LIGHTLY DOPED DRAIN REGION AND HEAVILY DOPING A GATE USING A SINGLE IMPLANT STEP

Patent #:	5989964	Issue Dt:	11/23/1999	Application #:	08818427	Filing Dt:	03/17/1997
Title:	POST-SPACER LDD IMPLANT FOR SHALLOW LDD TRANSISTOR

Patent #:	5885879	Issue Dt:	03/23/1999	Application #:	08822941	Filing Dt:	03/21/1997
Title:	THIN POLYSILICON MASKING TECHNIQUE FOR IMPROVED LITHOGRAPHY CONTROL

Patent #:	6372588	Issue Dt:	04/16/2002	Application #:	08837523	Filing Dt:	04/21/1997
Publication #:	US20010039094	Pub Dt:	11/08/2001
Title:	METHOD OF MAKING AN IGFET USING SOLID PHASE DIFFUSION TO DOPE THE GATE, SOURCE AND DRAIN

Patent #:	6057209	Issue Dt:	05/02/2000	Application #:	08891278	Filing Dt:	07/10/1997
Title:	A PROCESS OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A NITROGEN BEARING ISOLATION REGION

Patent #:	5970347	Issue Dt:	10/19/1999	Application #:	08896400	Filing Dt:	07/18/1997
Title:	HIGH PERFORMANCE MOSFET TRANSISTOR FABRICATION TECHNIQUE

Patent #:	6399505	Issue Dt:	06/04/2002	Application #:	08954175	Filing Dt:	10/20/1997
Publication #:	US20010041447	Pub Dt:	11/15/2001
Title:	METHOD AND SYSTEM FOR COPPER INTERCONNECT FORMATION

Patent #:	6159814	Issue Dt:	12/12/2000	Application #:	08968444	Filing Dt:	11/12/1997
Title:	SPACER FORMATION BY POLY STACK DOPANT PROFILE DESIGN

Patent #:	6069046	Issue Dt:	05/30/2000	Application #:	08979282	Filing Dt:	11/26/1997
Title:	TRANSISTOR FABRICATION EMPLOYING IMPLANTATION OF DOPANT INTO JUNCTIONS WITHOUT SUBJECTING SIDEWALL SURFACES OF A GATE CONDUCTOR TO ION BOMBARDMENT

Patent #:	6090712	Issue Dt:	07/18/2000	Application #:	08992489	Filing Dt:	12/18/1997
Title:	SHALLOW TRENCH ISOLATION FORMATION WITH NO POLISH STOP

Patent #:	6410967	Issue Dt:	06/25/2002	Application #:	09173273	Filing Dt:	10/15/1998
Title:	TRANSISTOR HAVING ENHANCED METAL SILICIDE AND A SELF-ALIGNED GATE ELECTRODE

Patent #:	6210999	Issue Dt:	04/03/2001	Application #:	09205047	Filing Dt:	12/04/1998
Title:	METHOD AND TEST STRUCTURE FOR LOW-TEMPERATURE INTEGRATION OF HIGH DIELECTRIC CONSTANT GATE DIELECTRICS INTO SELF-ALIGNED SEMICONDUCTOR DEVICES

Patent #:	7071101	Issue Dt:	07/04/2006	Application #:	09208325	Filing Dt:	12/09/1998
Title:	SACRIFICIAL TIN ARC LAYER FOR INCREASED PAD ETCH THROUGHPUT

Patent #:	6380091	Issue Dt:	04/30/2002	Application #:	09238050	Filing Dt:	01/27/1999
Title:	DUAL DAMASCENE ARRANGEMENT FOR METAL INTERCONNECTION WITH OXIDE DIELECTRIC LAYER AND LOW K DIELECTRIC CONSTANT LAYER

Patent #:	6265253	Issue Dt:	07/24/2001	Application #:	09305098	Filing Dt:	05/05/1999
Title:	ALUMINUM DISPOSABLE SPACER TO REDUCE MASK COUNT IN CMOS TRANSISTOR FORMATION

Patent #:	6127259	Issue Dt:	10/03/2000	Application #:	09372443	Filing Dt:	08/11/1999
Title:	PHOSPHORIC ACID PROCESS FOR REMOVAL OF CONTACT BARC LAYER

Patent #:	6358803	Issue Dt:	03/19/2002	Application #:	09489369	Filing Dt:	01/21/2000
Title:	Method of fabricating a deep source/drain

Patent #:	6724051	Issue Dt:	04/20/2004	Application #:	09679877	Filing Dt:	10/05/2000
Title:	NICKEL SILICIDE PROCESS USING NON-REACTIVE SPACER

Patent #:	6524947	Issue Dt:	02/25/2003	Application #:	09774800	Filing Dt:	02/01/2001
Title:	SLOTTED TRENCH DUAL INLAID STRUCTURE AND METHOD OF FORMING THEREOF

Patent #:	6531347	Issue Dt:	03/11/2003	Application #:	09776713	Filing Dt:	02/06/2001
Title:	RECESSED SOURCE DRAINS TO REDUCE FRINGING CAPACITANCE

Patent #:	6365450	Issue Dt:	04/02/2002	Application #:	09809706	Filing Dt:	03/15/2001
Title:	FABRICATION OF P-CHANNEL FIELD EFFECT TRANSISTOR WITH MINIMIZED DEGRADATION OF METAL OXIDE GATE

Patent #:	6518154	Issue Dt:	02/11/2003	Application #:	09813310	Filing Dt:	03/21/2001
Title:	METHOD OF FORMING SEMICONDUCTOR DEVICES WITH DIFFERENTLY COMPOSED METAL-BASED GATE ELECTRODES

Patent #:	6518646	Issue Dt:	02/11/2003	Application #:	09819615	Filing Dt:	03/29/2001
Title:	SEMICONDUCTOR DEVICE WITH VARIABLE COMPOSITION LOW-K INTER-LAYER DIELECTRIC AND METHOD OF MAKING

Patent #:	6686248	Issue Dt:	02/03/2004	Application #:	09825658	Filing Dt:	04/03/2001
Title:	METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A MOS TRANSISTOR WITH A HIGH DIELECTRIC CONSTANT MATERIAL

Patent #:	6635409	Issue Dt:	10/21/2003	Application #:	09902568	Filing Dt:	07/12/2001
Title:	METHOD OF STRENGTHENING PHOTORESIST TO PREVENT PATTERN COLLAPSE

Patent #:	6462416	Issue Dt:	10/08/2002	Application #:	09905469	Filing Dt:	07/13/2001
Title:	GRADATED BARRIER LAYER IN INTEGRATED CIRCUIT INTERCONNECTS

Patent #:	6500754	Issue Dt:	12/31/2002	Application #:	09999661	Filing Dt:	10/31/2001
Title:	ANNEAL HILLOCK SUPPRESSION METHOD IN INTEGRATED CIRCUIT INTERCONNECTS

Patent #:	6821713	Issue Dt:	11/23/2004	Application #:	10085242	Filing Dt:	02/27/2002
Title:	METHOD FOR LATERAL TRIMMING OF SPACERS

Patent #:	6573172	Issue Dt:	06/03/2003	Application #:	10244439	Filing Dt:	09/16/2002
Title:	METHODS FOR IMPROVING CARRIER MOBILITY OF PMOS AND NMOS DEVICES

Patent #:	6611029	Issue Dt:	08/26/2003	Application #:	10290158	Filing Dt:	11/08/2002
Title:	DOUBLE GATE SEMICONDUCTOR DEVICE HAVING SEPARATE GATES

Patent #:	6936480	Issue Dt:	08/30/2005	Application #:	10304573	Filing Dt:	11/26/2002
Publication #:	US20040023490	Pub Dt:	02/05/2004
Title:	METHOD OF CONTROLLING THE CHEMICAL MECHANICAL POLISHING OF STACKED LAYERS HAVING A SURFACE TOPOLOGY

Patent #:	6861350	Issue Dt:	03/01/2005	Application #:	10464508	Filing Dt:	06/19/2003
Title:	METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE COMPRISING SILICON-RICH TASIN METAL GATE ELECTRODE

Patent #:	6812119	Issue Dt:	11/02/2004	Application #:	10614052	Filing Dt:	07/08/2003
Title:	NARROW FINS BY OXIDATION IN DOUBLE-GATE FINFET

Patent #:	7034361	Issue Dt:	04/25/2006	Application #:	10653234	Filing Dt:	09/03/2003
Title:	NARROW BODY RAISED SOURCE/DRAIN METAL GATE MOSFET

Patent #:	7141502	Issue Dt:	11/28/2006	Application #:	10673597	Filing Dt:	09/29/2003
Title:	SLURRY-LESS POLISHING FOR REMOVAL OF EXCESS INTERCONNECT MATERIAL DURING FABRICATION OF A SILICON INTEGRATED CIRCUIT

Patent #:	7005358	Issue Dt:	02/28/2006	Application #:	10786401	Filing Dt:	02/25/2004
Publication #:	US20050026380	Pub Dt:	02/03/2005
Title:	TECHNIQUE FOR FORMING RECESSED SIDEWALL SPACERS FOR A POLYSILICON LINE

Patent #:	7091097	Issue Dt:	08/15/2006	Application #:	10933424	Filing Dt:	09/03/2004
Title:	END-OF-RANGE DEFECT MINIMIZATION IN SEMICONDUCTOR DEVICE

Patent #:	7473623	Issue Dt:	01/06/2009	Application #:	11428022	Filing Dt:	06/30/2006
Publication #:	US20080003789	Pub Dt:	01/03/2008
Title:	PROVIDING STRESS UNIFORMITY IN A SEMICONDUCTOR DEVICE

Patent #:	7531403	Issue Dt:	05/12/2009	Application #:	11538001	Filing Dt:	10/02/2006
Publication #:	US20080079074	Pub Dt:	04/03/2008
Title:	SOI SEMICONDUCTOR COMPONENTS AND METHODS FOR THEIR FABRICATION

Patent #:	7696052	Issue Dt:	04/13/2010	Application #:	11558006	Filing Dt:	11/09/2006
Publication #:	US20070228482	Pub Dt:	10/04/2007
Title:	TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS

Patent #:	7504287	Issue Dt:	03/17/2009	Application #:	11689764	Filing Dt:	03/22/2007
Publication #:	US20080233738	Pub Dt:	09/25/2008
Title:	METHODS FOR FABRICATING AN INTEGRATED CIRCUIT

Patent #:	7906424	Issue Dt:	03/15/2011	Application #:	11832486	Filing Dt:	08/01/2007
Publication #:	US20090032940	Pub Dt:	02/05/2009
Title:	CONDUCTOR BUMP METHOD AND APPARATUS

Patent #:	7754556	Issue Dt:	07/13/2010	Application #:	12027583	Filing Dt:	02/07/2008
Publication #:	US20090001484	Pub Dt:	01/01/2009
Title:	REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS

Patent #:	7816199	Issue Dt:	10/19/2010	Application #:	12037533	Filing Dt:	02/26/2008
Publication #:	US20090035924	Pub Dt:	02/05/2009
Title:	METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING AN IMPLANTATION OF IONS OF A NON-DOPING ELEMENT

Patent #:	7986008	Issue Dt:	07/26/2011	Application #:	12413185	Filing Dt:	03/27/2009
Publication #:	US20090184372	Pub Dt:	07/23/2009
Title:	SOI SEMICONDUCTOR COMPONENTS AND METHODS FOR THEIR FABRICATION

Patent #:	8318598	Issue Dt:	11/27/2012	Application #:	12537321	Filing Dt:	08/07/2009
Publication #:	US20100078823	Pub Dt:	04/01/2010
Title:	CONTACTS AND VIAS OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK AND DOUBLE EXPOSURE

Patent #:	8274120	Issue Dt:	09/25/2012	Application #:	12710744	Filing Dt:	02/23/2010
Publication #:	US20100155850	Pub Dt:	06/24/2010
Title:	TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS

Patent #:	8183605	Issue Dt:	05/22/2012	Application #:	12791290	Filing Dt:	06/01/2010
Publication #:	US20100237431	Pub Dt:	09/23/2010
Title:	REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS

Assignor

ADVANCED MICRO DEVICES, INC.

Exec Dt:

02/12/2016

Assignee

CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

515 LEGGET DRIVE

SUITE 704

OTTAWA, ONTARIO K2K3G4

Correspondence name and address
	RONAN O'BYRNE
	515 LEGGET DRIVE, SUITE 704
	CONVERSANT IPM
	OTTAWA, ONC K2K3G4

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