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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:011043/0794   Pages: 6
Recorded: 09/06/2000
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 75
1
Patent #:
5888579
Issue Dt:
03/30/1999
Application #:
08681718
Filing Dt:
07/29/1996
Title:
METHOD AND APPARATUS FOR PREVENTING PARTICLE CONTAMINATION IN A PROCESS CHAMBER
2
Patent #:
5930622
Issue Dt:
07/27/1999
Application #:
08954412
Filing Dt:
10/20/1997
Title:
METHOD FOR FORMING A DRAM CELL WITH A DOUBLE-CROWN SHAPED CAPACITOR
3
Patent #:
5866455
Issue Dt:
02/02/1999
Application #:
08954413
Filing Dt:
10/20/1997
Title:
METHOD FOR FORMING A DRAM CELL WITH A MULTIPLE PILLAR-SHAPED CAPACITOR
4
Patent #:
5834353
Issue Dt:
11/10/1998
Application #:
08954416
Filing Dt:
10/20/1997
Title:
METHOD OF MAKING DEEP SUB-MICRON METER MOSFET WITH A HIGH PERMITIVITY GATE DIELECTRIC
5
Patent #:
5807777
Issue Dt:
09/15/1998
Application #:
08962625
Filing Dt:
11/03/1997
Title:
METHOD OF MAKING A DOUBLE STAIR-LIKE CAPACITOR FOR A HIGH DENSITY DRAM CELL
6
Patent #:
6060394
Issue Dt:
05/09/2000
Application #:
08988034
Filing Dt:
12/10/1997
Title:
METHOD FOR FORMING SHALLOW TRENCH ISOLATION WITH GLOBAL PLANARIZATION
7
Patent #:
5966612
Issue Dt:
10/12/1999
Application #:
08995569
Filing Dt:
12/22/1997
Title:
METHOD OF MAKING A MULTIPLE MUSHROOM SHAPE CAPACITOR FOR HIGH DENSITY DRAMS
8
Patent #:
6146949
Issue Dt:
11/14/2000
Application #:
09104532
Filing Dt:
06/25/1998
Title:
METHOD OF MANUFACTURING MASK ROM DEVICES WITH SELF-ALIGNED CODING IMPLANT
9
Patent #:
6096613
Issue Dt:
08/01/2000
Application #:
09105337
Filing Dt:
06/26/1998
Title:
METHOD FOR POLY-BUFFERED LOCOS WITHOUT PITTING FORMATION
10
Patent #:
6137132
Issue Dt:
10/24/2000
Application #:
09109348
Filing Dt:
06/30/1998
Title:
HIGH DENSITY BURIED BIT LINE FLASH EEPROM MEMORY CELL WITH A SHALLOW TRENCH FLOATING GATE
11
Patent #:
6091119
Issue Dt:
07/18/2000
Application #:
09113931
Filing Dt:
07/10/1998
Title:
DOUBLE POLY-GATE HIGH DENSITY MULTI-STATE FLAT MASK ROM CELLS
12
Patent #:
6255682
Issue Dt:
07/03/2001
Application #:
09122813
Filing Dt:
07/27/1998
Title:
TRENCH DRAM CELLS WITH SELF-ALIGNED FIELD PLATE
13
Patent #:
6136697
Issue Dt:
10/24/2000
Application #:
09122825
Filing Dt:
07/27/1998
Title:
VOID-FREE AND VOLCANO-FREE TUNGSTEN-PLUG FOR ULSI INTERCONNECTION
14
Patent #:
6355540
Issue Dt:
03/12/2002
Application #:
09123746
Filing Dt:
07/27/1998
Publication #:
US20020004285
Pub Dt:
01/10/2002
Title:
STRESS-FREE SHALLOW TRENCH ISOLATION
15
Patent #:
6063683
Issue Dt:
05/16/2000
Application #:
09123748
Filing Dt:
07/27/1998
Title:
METHOD OF FABRICATING A SELF-ALIGNED CROWN-SHAPED CAPACITOR FOR HIGH DENSITY DRAM CELLS
16
Patent #:
5880508
Issue Dt:
03/09/1999
Application #:
09124409
Filing Dt:
07/29/1998
Title:
MOSFET WITH A HIGH PERMITIVITY GATE DIELECTRIC
17
Patent #:
5907782
Issue Dt:
05/25/1999
Application #:
09134885
Filing Dt:
08/15/1998
Title:
METHOD OF FORMING A MULTIPLE FIN-PILLAR CAPACITOR FOR A HIGH DENSITY DRAM CELL
18
Patent #:
6133118
Issue Dt:
10/17/2000
Application #:
09138298
Filing Dt:
08/21/1998
Title:
EDGE POLYSILICON BUFFER LOCOS ISOLATION
19
Patent #:
6295637
Issue Dt:
09/25/2001
Application #:
09189612
Filing Dt:
11/09/1998
Title:
SIMULATOR FOR THE POST-EXPOSURE BAKE OF CHEMICALLY AMPLIFIED RESISTS
20
Patent #:
6084261
Issue Dt:
07/04/2000
Application #:
09232552
Filing Dt:
01/18/1999
Title:
DRAM CELL WITH A FORK-SHAPED CAPACITOR
21
Patent #:
6207999
Issue Dt:
03/27/2001
Application #:
09238381
Filing Dt:
01/27/1999
Title:
DOUBLE CODING MASK READ ONLY MEMORY (MASK ROM) FOR MINIMIZING BAND-TO-BAND LEAKAGE
22
Patent #:
6090653
Issue Dt:
07/18/2000
Application #:
09243916
Filing Dt:
02/03/1999
Title:
METHOD OF MANUFACTURING CMOS TRANSISTORS
23
Patent #:
6117712
Issue Dt:
09/12/2000
Application #:
09248955
Filing Dt:
02/12/1999
Title:
METHOD OF FORMING ULTRA-SHORT CHANNEL AND ELEVATED S/D MOSFETS WITH A METAL GATE ON SOI SUBSTRATE
24
Patent #:
6281542
Issue Dt:
08/28/2001
Application #:
09249840
Filing Dt:
02/15/1999
Title:
FLOWER-LIKE CAPACITOR STRUCTURE FOR A MEMORY CELL
25
Patent #:
6008090
Issue Dt:
12/28/1999
Application #:
09261027
Filing Dt:
03/02/1999
Title:
METHOD OF FORMING HIGH DENSITY FLASH MEMORIES WITH HIGH CAPACITIVE-COUPING RATIO AND HIGH SPEED OPERATION
26
Patent #:
6259130
Issue Dt:
07/10/2001
Application #:
09265062
Filing Dt:
03/09/1999
Title:
HIGH DENSITY FLASH MEMORIES WITH HIGH CAPACITIVE-COUPING RATIO AND HIGH SPEED OPERATION
27
Patent #:
6100135
Issue Dt:
08/08/2000
Application #:
09266352
Filing Dt:
03/11/1999
Title:
METHOD OF FORMING A CROWN-FIN SHAPED CAPACITOR FOR A HIGH DENSITY DRAM CELL
28
Patent #:
5998264
Issue Dt:
12/07/1999
Application #:
09266552
Filing Dt:
03/11/1999
Title:
METHOD OF FORMING HIGH DENSITY FLASH MEMORIES WITH MIM STRUCTURE
29
Patent #:
6117731
Issue Dt:
09/12/2000
Application #:
09270908
Filing Dt:
03/15/1999
Title:
METHOD OF FORMING HIGH CAPACITIVE-COUPLING RATIO AND HIGH SPEED FLASH MEMORIES WITH A TEXTURED TUNNEL OXIDE
30
Patent #:
6153467
Issue Dt:
11/28/2000
Application #:
09271736
Filing Dt:
03/18/1999
Title:
METHOD OF FABRICATING HIGH DENSITY BURIED BIT LINE FLASH EEPROM MEMORY CELL WITH A SHALLOW TRENCH FLOATING GATE
31
Patent #:
6555438
Issue Dt:
04/29/2003
Application #:
09275134
Filing Dt:
03/23/1999
Title:
METHOD FOR FABRICATING MOSFETS WITH A RECESSED SELF-ALIGNED SILICIDE CONTACT AND EXTENDED SOURCE/DRAIN JUNCTIONS
32
Patent #:
6348390
Issue Dt:
02/19/2002
Application #:
09275135
Filing Dt:
03/23/1999
Title:
METHOD FOR FABRICATING MOSFETS WITH A RECESSED SELF-ALIGNED SILICIDE CONTACT AND EXTENDED SOURCE/DRAIN JUNCTIONS
33
Patent #:
6432785
Issue Dt:
08/13/2002
Application #:
09275136
Filing Dt:
03/23/1999
Title:
METHOD FOR FABRICATING ULTRA SHORT CHANNEL PMOSFET WITH BURIED SOURCE/DRAIN JUNCTIONS AND SELF-ALIGNED SILICIDE
34
Patent #:
6184087
Issue Dt:
02/06/2001
Application #:
09283405
Filing Dt:
04/01/1999
Title:
METHOD FOR FORMING HIGH DENSITY NONVOLATILE MEMORIES WITH HIGH CAPACITIVE-COUPLING RATIO
35
Patent #:
6211016
Issue Dt:
04/03/2001
Application #:
09283406
Filing Dt:
04/01/1999
Title:
METHOD FOR FORMING HIGH DENSITY NONVOLATILE MEMORIES WITH HIGH CAPACITIVE-COUPLING RATIO
36
Patent #:
6187619
Issue Dt:
02/13/2001
Application #:
09288948
Filing Dt:
04/09/1999
Title:
METHOD TO FABRICATE SHORT-CHANNEL MOSFETS WITH AN IMPROVEMENT IN ESD RESISTANCE
37
Patent #:
6046090
Issue Dt:
04/04/2000
Application #:
09291264
Filing Dt:
04/14/1999
Title:
PROCESS TO FABRICATE ULTRA-SHORT CHANNEL MOSFETS WITH SELF-ALIGNED SILICIDE CONTACT
38
Patent #:
6136636
Issue Dt:
10/24/2000
Application #:
09291265
Filing Dt:
04/14/1999
Title:
METHOD OF MANUFACTURING DEEP SUB-MICRON CMOS TRANSISTORS
39
Patent #:
6069044
Issue Dt:
05/30/2000
Application #:
09291270
Filing Dt:
04/14/1999
Title:
PROCESS TO FABRICATE ULTRA-SHORT CHANNEL NMOSFETS WITH SELF-ALIGNED SILICIDE CONTACT
40
Patent #:
6284612
Issue Dt:
09/04/2001
Application #:
09291271
Filing Dt:
04/14/1999
Title:
PROCESS TO FABRICATE ULTRA-SHORT CHANNEL MOSFETS WITH SELF-ALIGNED SILICIDE CONTACT
41
Patent #:
6211002
Issue Dt:
04/03/2001
Application #:
09292478
Filing Dt:
04/15/1999
Title:
CMOS PROCESS FOR FORMING PLANARIZED TWIN WELLS
42
Patent #:
6265263
Issue Dt:
07/24/2001
Application #:
09293454
Filing Dt:
04/16/1999
Title:
METHOD FOR FORMING A DRAM CAPACITOR WITH POROUS STORAGE NODE AND RUGGED SIDEWALLS
43
Patent #:
6268245
Issue Dt:
07/31/2001
Application #:
09298927
Filing Dt:
04/22/1999
Title:
METHOD FOR FORMING A DRAM CELL WITH A RAGGED POLYSILICON CROWN-SHAPED CAPACITOR
44
Patent #:
6090663
Issue Dt:
07/18/2000
Application #:
09298929
Filing Dt:
04/22/1999
Title:
METHOD FOR FORMING A HIGH-DENSITY DRAM CELL WITH A RUGGED POLYSILICON CUP-SHAPED CAPACITOR
45
Patent #:
6008514
Issue Dt:
12/28/1999
Application #:
09300638
Filing Dt:
04/27/1999
Title:
DOUBLE-CROWN SHAPE CAPACITOR WITH HIGH-DIELECTRIC CONSTANT MATERIAL
46
Patent #:
6177323
Issue Dt:
01/23/2001
Application #:
09303143
Filing Dt:
04/30/1999
Title:
METHOD TO FORM MOSFET WITH AN ELEVATED SOURCE/DRAIN FOR PMOSFET
47
Patent #:
6294416
Issue Dt:
09/25/2001
Application #:
09307629
Filing Dt:
05/07/1999
Title:
METHOD OF FABRICATING CMOS TRANSISTORS WITH SELF-ALIGNED PLANARIZATION TWIN-WELL BY USING FEWER MASK COUNTS
48
Patent #:
6156613
Issue Dt:
12/05/2000
Application #:
09307630
Filing Dt:
05/07/1999
Title:
METHOD TO FORM MOSFET WITH AN ELEVATED SOURCE/DRAIN
49
Patent #:
6274428
Issue Dt:
08/14/2001
Application #:
09310487
Filing Dt:
05/12/1999
Title:
METHOD FOR FORMING A RAGGED POLYSILICON CROWN-SHAPED CAPACITOR FOR A MEMORY CELL
50
Patent #:
6329264
Issue Dt:
12/11/2001
Application #:
09310888
Filing Dt:
05/12/1999
Title:
METHOD FOR FORMING A RAGGED POLYSILCON CROWN-SHAPED CAPACITOR FOR A MEMORY CELL
51
Patent #:
6114214
Issue Dt:
09/05/2000
Application #:
09310889
Filing Dt:
05/12/1999
Title:
METHOD FOR FORMING A HIGH-DENSITY DRAM CELL WITH A DOUBLE-CROWN RUGGED POLYSILICON CAPACITOR
52
Patent #:
6091098
Issue Dt:
07/18/2000
Application #:
09310890
Filing Dt:
05/12/1999
Title:
DOUBLE-CROWN RUGGED POLYSILICON CAPACITOR
53
Patent #:
6204124
Issue Dt:
03/20/2001
Application #:
09313084
Filing Dt:
05/17/1999
Title:
METHOD FOR FORMING HIGH DENSITY NONVOLATILE MEMORIES WITH HIGH CAPACITIVE-COUPLING RATIO
54
Patent #:
6303417
Issue Dt:
10/16/2001
Application #:
09313085
Filing Dt:
05/17/1999
Title:
METHOD OF FORMING SELF-ALIGNED PLANARIZATION TWIN-WELL BY USING FEWER MASK COUNTS FOR CMOS TRANSISTORS
55
Patent #:
6133104
Issue Dt:
10/17/2000
Application #:
09323772
Filing Dt:
06/01/1999
Title:
METHOD OF ELIMINATING BURIED CONTACT TRENCH IN MOSFET DEVICES WITH SELF-ALIGNED SILICIDE INCLUDING A SILICON CONNECTION TO THE BURIED CONTACT REGION WHICH COMPRISES A DOPED SILICON SIDEWALL
56
Patent #:
6211556
Issue Dt:
04/03/2001
Application #:
09323773
Filing Dt:
06/01/1999
Title:
ELIMINATING BURIED CONTACT TRENCH IN MOSFET DEVICES HAVING SELF-ALIGNED SILICIDE
57
Patent #:
6255167
Issue Dt:
07/03/2001
Application #:
09325810
Filing Dt:
06/04/1999
Title:
METHOD OF FORMING HIGH DENSITY BURIED BIT LILNE FLASH EEPROM MEMORY CELL WITH A SHALLOW TRENCH FLOATING GATE
58
Patent #:
6548362
Issue Dt:
04/15/2003
Application #:
09325811
Filing Dt:
06/04/1999
Title:
METHOD OF FORMING MOSFET WITH BURIED CONTACT AND AIR-GAP GATE STRUCTURE
59
Patent #:
6207505
Issue Dt:
03/27/2001
Application #:
09326857
Filing Dt:
06/07/1999
Title:
METHOD FOR FORMING HIGH DENSITY NONVOLATILE MEMORIES WITH HIGH CAPACITIVE-COUPLING RATIO
60
Patent #:
NONE
Issue Dt:
Application #:
09326858
Filing Dt:
06/07/1999
Publication #:
US20010012675
Pub Dt:
08/09/2001
Title:
SHALLOW TRENCH ISOLATION PROCESS
61
Patent #:
6117756
Issue Dt:
09/12/2000
Application #:
09336869
Filing Dt:
06/18/1999
Title:
METHOD OF FORMING HIGH DENSITY AND LOW POWER FLASH MEMORIES WITH A HIGH CAPACITIVE-COUPLING RATIO
62
Patent #:
6316316
Issue Dt:
11/13/2001
Application #:
09336870
Filing Dt:
06/18/1999
Title:
METHOD OF FORMING HIGH DENSITY AND LOW POWER FLASH MEMORIES WITH A HIGH CAPACITIVE-COUPLING RATIO
63
Patent #:
6323094
Issue Dt:
11/27/2001
Application #:
09345925
Filing Dt:
07/01/1999
Title:
METHOD TO FABRICATE DEEP SUB-UM CMOSFETS
64
Patent #:
6127712
Issue Dt:
10/03/2000
Application #:
09346041
Filing Dt:
07/06/1999
Title:
MOSFET WITH BURIED CONTACT AND AIR-GAP GATE STRUCTURE
65
Patent #:
6162681
Issue Dt:
12/19/2000
Application #:
09346042
Filing Dt:
07/06/1999
Title:
DRAM CELL WITH A FORK-SHAPED CAPACITOR
66
Patent #:
6251731
Issue Dt:
06/26/2001
Application #:
09351873
Filing Dt:
07/13/1999
Title:
METHOD FOR FABRICATING HIGH-DENSITY AND HIGH-SPEED NAND-TYPE MASK ROMS
67
Patent #:
6265259
Issue Dt:
07/24/2001
Application #:
09351876
Filing Dt:
07/13/1999
Title:
METHOD TO FABRICATE DEEP SUB-UM CMOSFETS
68
Patent #:
6207526
Issue Dt:
03/27/2001
Application #:
09353508
Filing Dt:
07/14/1999
Title:
METHOD OF FABRICATING AN EXTENDED SELF-ALIGNED CROWN-SHAPED RUGGED CAPACITOR FOR HIGH DENSITY DRAM CELLS
69
Patent #:
6232648
Issue Dt:
05/15/2001
Application #:
09353509
Filing Dt:
07/14/1999
Title:
EXTENDED SELF-ALIGNED CROWN-SHAPED RUGGED CAPACITOR FOR HIGH DENSITY DRAM CELLS
70
Patent #:
6358818
Issue Dt:
03/19/2002
Application #:
09361447
Filing Dt:
07/26/1999
Title:
METHOD FOR FORMING TRENCH ISOLATION REGIONS
71
Patent #:
6171893
Issue Dt:
01/09/2001
Application #:
09366606
Filing Dt:
08/03/1999
Title:
METHOD FOR FORMING SELF-ALIGNED SILICIDED MOS TRANSISTORS WITH ESD PROTECTION IMPROVEMENT
72
Patent #:
6214696
Issue Dt:
04/10/2001
Application #:
09394296
Filing Dt:
09/10/1999
Title:
METHOD OF FABRICATING DEEP-SHALLOW TRENCH ISOLATION
73
Patent #:
6190977
Issue Dt:
02/20/2001
Application #:
09439431
Filing Dt:
11/15/1999
Title:
METHOD FOR FORMING MOSFET WITH AN ELEVATED SOURCE/DRAIN
74
Patent #:
6294797
Issue Dt:
09/25/2001
Application #:
09439432
Filing Dt:
11/15/1999
Title:
MOSFET WITH AN ELEVATED SOURCE/DRAIN
75
Patent #:
6342422
Issue Dt:
01/29/2002
Application #:
09439433
Filing Dt:
11/15/1999
Title:
METHOD FOR FORMING MOSFET WITH AN ELEVATED SOURCEDDD/DRAIN
Assignor
1
TEXAS INSTRUMENTS-ACER INCORPORATED
Exec Dt:
06/30/2000
Assignee
1
ACER SEMICONDUCTOR MANUFACTURING INC.
SCIENCE-BASED INDUSTRIAL PARK
NO. 6, CREATION RD. II
HSINCHU, TAIWAN R.O.C
Correspondence name and address
THOMAS, KAYDEN, HORSTEMEYER, ET AL
DANIEL R. MCCLURE
100 GALLERIA PARKWAY
SUITE 1750
ATLANTA, GEORGIA 30339

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