Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 063069/0796 | |
| Pages: | 7 |
| | Recorded: | 03/13/2023 | | |
| Attorney Dkt #: | 095714-1554 |
| Conveyance: | CORRECTIVE ASSIGNMENT TO CORRECT THE OMISSION SECOND ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 058296 FRAME: 0946. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT . |
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Total properties:
1
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Patent #:
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Issue Dt:
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04/11/2023
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Application #:
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17504207
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Filing Dt:
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10/18/2021
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Publication #:
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Pub Dt:
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02/03/2022
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Title:
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METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD FOR PACKAGING SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION (STI)
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Assignees
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| NO. 8 LI-HSIN RD. 6, SCIENCE BASED INDUSTRIAL PARK |
| HSINCHU, TAIWAN 300 |
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| NO. 1, SEC. 4, ROOSEVELT ROAD |
| TAIPEI, TAIWAN |
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Correspondence name and address
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MCDERMOTT WILL & EMERY LLP
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500 NORTH CAPITOL STREET, NW
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WASHINGTON, DC 20001
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