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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:016087/0799   Pages: 6
Recorded: 06/06/2005
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 10
1
Patent #:
Issue Dt:
05/09/1989
Application #:
06879738
Filing Dt:
06/27/1986
Title:
MULTILEVEL INTEGRATED CIRCUITS EMPLOYING FUSED OXIDE LAYERS
2
Patent #:
Issue Dt:
05/31/1994
Application #:
08034451
Filing Dt:
03/19/1993
Title:
DYNAMIC CONTROL OF CONFIGURABLE LOGIC
3
Patent #:
Issue Dt:
03/07/1995
Application #:
08086222
Filing Dt:
07/02/1993
Title:
DYNAMIC RANDOM ACCESS MEMORY
4
Patent #:
Issue Dt:
12/20/1994
Application #:
08110897
Filing Dt:
08/24/1993
Title:
DYNAMIC CONTROL OF CONFIGURABLE LOGIC
5
Patent #:
Issue Dt:
08/12/1997
Application #:
08353788
Filing Dt:
12/12/1994
Title:
METHOD OF FORMING A DYNAMIC RANDOM ACCESS MEMORY
6
Patent #:
Issue Dt:
08/18/1998
Application #:
08609401
Filing Dt:
03/01/1996
Title:
DYNAMIC RANDOM ACCESS MEMORY
7
Patent #:
Issue Dt:
01/01/2002
Application #:
08792419
Filing Dt:
02/03/1997
Title:
DYNAMIC RANDOM ACCESS MEMORY
8
Patent #:
Issue Dt:
07/02/2002
Application #:
08794004
Filing Dt:
02/03/1997
Title:
DYNAMIC RANDOM ACCESS MEMORY
9
Patent #:
Issue Dt:
06/05/2001
Application #:
08811073
Filing Dt:
03/03/1997
Title:
MULTI-SIDED CAPACITOR IN AN INTEGRATED CIRCUIT
10
Patent #:
Issue Dt:
06/25/2002
Application #:
09865926
Filing Dt:
05/24/2001
Publication #:
Pub Dt:
11/01/2001
Title:
METHOD FO FORMING A SUBMERGED SEMICONDUCTOR STRUCTURE.
Assignor
1
Exec Dt:
01/22/2005
Assignee
1
2215-B RENAISSANCE DRIVE
SUITE 5
LAS VEGAS, NEVADA 89119
Correspondence name and address
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005

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