Patent Assignment Details
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| Reel/Frame: | 011462/0810 | |
| Pages: | 4 |
| | Recorded: | 01/11/2001 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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10/14/2003
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Application #:
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09759028
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Filing Dt:
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01/11/2001
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Publication #:
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Pub Dt:
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08/23/2001
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Title:
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OPTIMIZED SILICON WAFER GETTERING FOR ADVANCED SEMICONDUCTOR DEVICES
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Assignee
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| 4111 N.E., 112TH AVENUE |
| VANCOUVER, WASHINGTON 98682 |
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Correspondence name and address
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KOLISCH, HARTWELL, DICKINSON & ET AL
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MICHAEL M. HALL
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520 S.W. YAMHILL STREET, SUITE 200
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PORTLAND, OR 97204
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