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Total properties:
32
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|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09267308
|
Filing Dt:
|
03/12/1999
|
|
Title:
|
PROCESS FOR FORMING A LOW RESISTIVITY TITANIUM SILICIDE LAYER ON A SILICON SEMICONDUCTOR SUBSTRATE AND THE RESULTING DEVICE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
09673203
|
Filing Dt:
|
10/12/2000
|
|
Title:
|
METHOD OF MANUFACTURING A VERTICAL METAL CONNECTION IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09790259
|
Filing Dt:
|
02/21/2001
|
|
Title:
|
PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09816485
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Filing Dt:
|
03/23/2001
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|
Publication #:
|
|
Pub Dt:
|
11/29/2001
| | | | |
|
Title:
|
METHOD OF FORMING AN INSULATING ZONE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
09823274
|
Filing Dt:
|
03/29/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
|
Title:
|
MOS TRANSISTOR IN AN INTEGRATED CIRCUIT AND ACTIVE AREA FORMING METHOD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
09858400
|
Filing Dt:
|
05/16/2001
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
|
Title:
|
PROCESS FOR FORMING A LOW RESISTIVITY TITANIUM SILICIDE LAYER ON A SILICON SEMICONDUCTOR SUBSTRATE AND THE RESULTING DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
09933784
|
Filing Dt:
|
08/21/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2002
| | | | |
|
Title:
|
PROCESS FOR FORMING SHALLOW ISOLATING REGIONS IN AN INTEGRATED CIRCUIT AND AN INTEGRATED CIRCUIT THUS FORMED
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10479639
|
Filing Dt:
|
12/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/29/2004
| | | | |
|
Title:
|
DEEP INSULATING TRENCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
10526422
|
Filing Dt:
|
07/05/2006
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
|
Title:
|
METHOD FOR FABRICATION OF IN-LAID METAL INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
10589275
|
Filing Dt:
|
08/10/2006
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2007
| | | | |
|
Title:
|
PROCESS FOR FABRICATING AN ELECTRONIC INTEGRATED CIRCUIT AND ELECTRONIC INTEGRATED CIRCUIT THUS OBTAINED
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10651492
|
Filing Dt:
|
08/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
PROCESS FOR FABRICATING AN ELECTRICAL CIRCUIT COMPRISING A POLISHING STEP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10714442
|
Filing Dt:
|
11/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/22/2004
| | | | |
|
Title:
|
ELECTRICAL CONNECTION DEVICE BETWEEN TWO TRACKS OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
10781565
|
Filing Dt:
|
02/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/18/2004
| | | | |
|
Title:
|
PROCESS FOR FABRICATING AN INTEGRATED ELECTRONIC CIRCUIT THAT INCORPORATES AIR GAPS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10871542
|
Filing Dt:
|
06/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
|
Title:
|
Method for the formation of silicides
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2007
|
Application #:
|
11110359
|
Filing Dt:
|
04/20/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2005
| | | | |
|
Title:
|
METHOD OF FABRICATING AN INTEGRATED CIRCUIT INCLUDING HOLLOW ISOLATING TRENCHES AND CORRESPONDING INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2009
|
Application #:
|
11456657
|
Filing Dt:
|
07/11/2006
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2007
| | | | |
|
Title:
|
INTEGRATION CONTROL AND RELIABILITY ENHANCEMENT OF INTERCONNECT AIR CAVITIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2009
|
Application #:
|
11482520
|
Filing Dt:
|
07/07/2006
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
|
Title:
|
CONTROLLING LATERAL DISTRIBUTION OF AIR GAPS IN INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
11570731
|
Filing Dt:
|
11/06/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
|
Title:
|
INTEGRATED CIRCUIT COMPRISING A CAPACITOR WITH METAL ELECTRODES AND PROCESS FOR FABRICATING SUCH A CAPACITOR
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11722974
|
Filing Dt:
|
03/19/2010
|
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
|
Title:
|
ANTI-FUSE CELL AND ITS MANUFACTURING PROCESS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11744574
|
Filing Dt:
|
05/04/2007
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2007
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR FORMING A SEMICONDUCTOR SUBSTRATE WITH A LAYER STRUCTURE OF ACTIVATED DOPANTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
11912126
|
Filing Dt:
|
10/19/2007
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
|
Title:
|
Apparatus for Cleaning of Circuit Substrates
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11960382
|
Filing Dt:
|
12/19/2007
|
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
|
Title:
|
DUAL GATE FIELD EFFECT TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
11991041
|
Filing Dt:
|
07/20/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
|
Title:
|
Microelectromechanical device packaging with an anchored cap and its manufacture
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
12065179
|
Filing Dt:
|
02/28/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A COUPLED DIELECTRIC LAYER AND METAL LAYER, METHOD OF FABRICATION THEREOF, AND MATERIAL FOR COUPLING A DIELECTRIC LAYER AND A METAL LAYER IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12065190
|
Filing Dt:
|
02/28/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
|
Title:
|
CAPPING LAYER FORMATION ONTO A DUAL DAMESCENE INTERCONNECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
12158989
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
|
Title:
|
ON-CHIP INTERCONNECT-STACK COOLING USING SACRIFICIAL INTERCONNECT SEGMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
12161456
|
Filing Dt:
|
12/08/2009
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
INTEGRATION OF SELF-ALIGNED TRENCHES IN-BETWEEN METAL LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
|
Application #:
|
12280477
|
Filing Dt:
|
08/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A COUPLED DIELECTRIC LAYER AND METAL LAYER, METHOD OF FABRICATION THEREOF, AND PASSIVATING COUPLING MATERIAL COMPRISING MULTIPLE ORGANIC COMPONENTS FOR USE IN A SEMICONDUCTOR DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12280978
|
Filing Dt:
|
03/25/2009
|
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
|
Title:
|
METHOD FOR FORMING METAL INTERCONNECTS IN A DIELECTRIC MATERIAL
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12296402
|
Filing Dt:
|
10/07/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/26/2009
| | | | |
|
Title:
|
CO-INTEGRATION OF MULTI-GATE FET WITH OTHER FET DEVICES IN CMOS TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2011
|
Application #:
|
12439910
|
Filing Dt:
|
03/04/2009
|
|
Publication #:
|
|
Pub Dt:
|
11/05/2009
| | | | |
|
Title:
|
CUSIN/SIN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
12439919
|
Filing Dt:
|
03/04/2009
|
|
Publication #:
|
|
Pub Dt:
|
11/05/2009
| | | | |
|
Title:
|
CONTROL OF CARBON NANOSTRUCTURE GROWTH IN AN INTERCONNECT STRUCTURE
|
|
