Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 013169/0836 | |
| Pages: | 8 |
| | Recorded: | 08/12/2002 | | |
| Conveyance: | SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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05/04/1999
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Application #:
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08804524
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Filing Dt:
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02/21/1997
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Title:
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A SYSTEM AND METHOD FOR EXTRACTING PARASITIC IMPEDANCE FROM AN INTEGRATED CIRCUIT LAYOUT
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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08937393
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Filing Dt:
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09/25/1997
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Title:
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METHODS FOR DETERMINING ON-CHIP INTERCONNECT PROCESS PARAMETERS
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09244616
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Filing Dt:
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02/04/1999
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Title:
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METHODS FOR DETERMINING ON-CHIP INTERCONNECT PROCESS PARAMETERS
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09350966
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Filing Dt:
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07/09/1999
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Title:
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METHOD AND SYSTEM FOR EXTRACTION OF PARASITIC INTERCONNECT IMPEDANCE INCLUDING INDUCTANCE
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09405510
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Filing Dt:
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09/23/1999
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Title:
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METHOD FOR MODELING A CONDUCTIVE SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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Application #:
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UNAVAILABLE
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Filing Dt:
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Title:
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Assignee
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| 3003 TASMAN DR. |
| LOAN DOCUMENTATION HA155 |
| SANTA CLARA, CALIFORNIA 95054 |
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Correspondence name and address
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SILICON VALLEY BANK
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PIA A. PENA
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LOAN DOCUMENTATION HA155
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3003 TASMAN DR.
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SANTA CLARA, CA 95054
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