|
Total properties:
16
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
13512507
|
Filing Dt:
|
05/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
|
Title:
|
METHOD FOR ALLOCATING ADDRESSES TO DATA BUFFERS IN DISTRIBUTED BUFFER CHIPSET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13579201
|
Filing Dt:
|
08/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
|
Title:
|
WRITE CIRCUIT, READ CIRCUIT, MEMORY BUFFER AND MEMORY MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
13586317
|
Filing Dt:
|
08/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
|
Title:
|
DEVICE REQUIRING ADDRESS ALLOCATION, DEVICE SYSTEM AND ADDRESS ALLOCATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
13715555
|
Filing Dt:
|
12/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
|
Title:
|
VOLTAGE AND TIMING CALIBRATION METHOD USED IN MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2015
|
Application #:
|
13813355
|
Filing Dt:
|
01/30/2013
|
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
|
Title:
|
DATA READ/WRITE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2016
|
Application #:
|
14067468
|
Filing Dt:
|
10/30/2013
|
|
Publication #:
|
|
Pub Dt:
|
04/02/2015
| | | | |
|
Title:
|
WINDING AND METHOD FOR PREPARING A WINDING APPLIED TO AN INDUCTIVE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
14102424
|
Filing Dt:
|
12/10/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
|
Title:
|
WIDEBAND ACTIVE BALUN LNA TOPOLOGY WITH NARROW-BAND FILTERING AND NOISE CANCELLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
14109195
|
Filing Dt:
|
12/17/2013
|
|
Publication #:
|
|
Pub Dt:
|
01/29/2015
| | | | |
|
Title:
|
ADAPTIVE HARMONIC REJECTION RECEIVING DEVICE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2016
|
Application #:
|
14153093
|
Filing Dt:
|
01/13/2014
|
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
|
Title:
|
Signal Generator, Electronic System Comprising the Signal Generator and Method of Generating Signals
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2016
|
Application #:
|
14194726
|
Filing Dt:
|
03/01/2014
|
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
|
Title:
|
Voltage Regulator and Method of Regulating Voltage
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2016
|
Application #:
|
14337839
|
Filing Dt:
|
07/22/2014
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2015
| | | | |
|
Title:
|
Device and method for clock signal loss detection
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2017
|
Application #:
|
14977656
|
Filing Dt:
|
12/22/2015
|
|
Publication #:
|
|
Pub Dt:
|
06/08/2017
| | | | |
|
Title:
|
NOISE POWER ESTIMATOR, RECEIVER AND METHOD FOR NOISE POWER ESTIMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2019
|
Application #:
|
15068657
|
Filing Dt:
|
03/14/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2017
| | | | |
|
Title:
|
METHOD AND DEVICE FOR PROTECTING DYNAMIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2017
|
Application #:
|
15161764
|
Filing Dt:
|
05/23/2016
|
|
Publication #:
|
|
Pub Dt:
|
03/23/2017
| | | | |
|
Title:
|
DIGITAL DELAY-LOCKED LOOP AND LOCKING METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15219092
|
Filing Dt:
|
07/25/2016
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2018
| | | | |
|
Title:
|
CIRCUIT AND METHOD FOR REDUCING MISMATCH FOR COMBINED CLOCK SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2018
|
Application #:
|
15637623
|
Filing Dt:
|
06/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/14/2018
| | | | |
|
Title:
|
SIGNAL TRANSMITTING CIRCUIT
|
|
