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Reel/Frame:	035225/0839			Pages:	82
		Recorded:	03/19/2015
Attorney Dkt #:	40767.149
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 56

1

Patent #:	6628660	Issue Dt:	09/30/2003	Application #:	09330753	Filing Dt:	06/11/1999
Title:	FINITE STATE MACHINE WITH ASSOCIATED MEMORY

2

Patent #:	6028789	Issue Dt:	02/22/2000	Application #:	09334051	Filing Dt:	06/15/1999
Title:	ZERO-POWER CMOS NON VOLATILE MEMORY CELL HAVING AN AVALANCHE INJECTION ELEMENT

3

Patent #:	6034893	Issue Dt:	03/07/2000	Application #:	09334052	Filing Dt:	06/15/1999
Title:	NON-VOLATILE MEMORY CELL HAVING DUAL AVALANCHE INJECTION ELEMENTS

4

Patent #:	6404226	Issue Dt:	06/11/2002	Application #:	09400029	Filing Dt:	09/21/1999
Title:	INTEGRATED CIRCUIT WITH STANDARD CELL LOGIC AND SPARE GATES

5

Patent #:	6550030	Issue Dt:	04/15/2003	Application #:	09405958	Filing Dt:	09/27/1999
Title:	ON-LINE TESTING OF THE PROGRAMMABLE LOGIC BLOCKS IN FIELD PROGRAMMABLE GATE ARRAYS

6

Patent #:	6574761	Issue Dt:	06/03/2003	Application #:	09406219	Filing Dt:	09/27/1999
Title:	ON-LINE TESTING OF THE PROGRAMMABLE INTERCONNECT NETWORK IN FIELD PROGRAMMABLE GATE ARRAYS

7

Patent #:	6191609	Issue Dt:	02/20/2001	Application #:	09433642	Filing Dt:	11/03/1999
Title:	COMBINATION OF GLOBAL CLOCK AND LOCALIZED CLOCKS

8

Patent #:	6278311	Issue Dt:	08/21/2001	Application #:	09440207	Filing Dt:	11/15/1999
Title:	METHOD FOR MINIMIZING INSTANTANEOUS CURRENTS WHEN DRIVING BUS SIGNALS

9

Patent #:	6294925	Issue Dt:	09/25/2001	Application #:	09440460	Filing Dt:	11/15/1999
Title:	PROGRAMMABLE LOGIC DEVICE

10

Patent #:	6208559	Issue Dt:	03/27/2001	Application #:	09441220	Filing Dt:	11/15/1999
Title:	METHOD OF OPERATING EEPROM MEMORY CELLS HAVING TRANSISTORS WITH THIN GATE OXIDE AND REDUCED DISTURB

11

Patent #:	6137738	Issue Dt:	10/24/2000	Application #:	09452017	Filing Dt:	11/30/1999
Title:	METHOD FOR IN-SYSTEM PROGRAMMING OF SERIALLY CONFIGURED EEPROMS USING A JTAG INTERFACE OF A FIELD PROGRAMMABLE GATE ARRAY

12

Patent #:	6326808	Issue Dt:	12/04/2001	Application #:	09454322	Filing Dt:	12/03/1999
Title:	INVERSION OF PRODUCT TERM LINE BEFORE OR LOGIC IN A PROGRAMMABLE LOGIC DEVICE (PLD)

13

Patent #:	6150842	Issue Dt:	11/21/2000	Application #:	09472645	Filing Dt:	12/27/1999
Title:	VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS

14

Patent #:	6362684	Issue Dt:	03/26/2002	Application #:	09506180	Filing Dt:	02/17/2000
Title:	Amplifier having an adjust resistor network

15

Patent #:	6424209	Issue Dt:	07/23/2002	Application #:	09507580	Filing Dt:	02/18/2000
Title:	INTEGRATED PROGRAMMABLE CONTINUOUS TIME FILTER WITH PROGRAMMABLE CAPACITOR ARRAYS

16

Patent #:	6351157	Issue Dt:	02/26/2002	Application #:	09548171	Filing Dt:	04/13/2000
Title:	Output buffer for making a high voltage (5.0 volt) compatible input/output in a low voltage (2.5volt)semiconductor process

17

Patent #:	6288937	Issue Dt:	09/11/2001	Application #:	09567898	Filing Dt:	05/10/2000
Title:	Decoded generic routing pool

18

Patent #:	6570212	Issue Dt:	05/27/2003	Application #:	09578086	Filing Dt:	05/24/2000
Title:	COMPLEMENTARY AVALANCHE INJECTION EEPROM CELL

19

Patent #:	6292930	Issue Dt:	09/18/2001	Application #:	09603119	Filing Dt:	06/22/2000
Title:	Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources

20

Patent #:	6216257	Issue Dt:	04/10/2001	Application #:	09603807	Filing Dt:	06/26/2000
Title:	AN FPGA DEVICE AND METHOD THAT INCLUDES A VARIABLE GRAIN FUNCTION ARCHITECTURE FOR IMPLEMENTING CONFIGURATION LOGIC BLOCKS AND A COMPLIMENTARY VARIABLE LENGTH INTERCONNECT ARCHITECTURE FOR PROVIDING CONFIGURABLE ROUTING BETWEEN CONFIGURATION LOGIC BLOCKS

21

Patent #:	6530049	Issue Dt:	03/04/2003	Application #:	09611449	Filing Dt:	07/06/2000
Title:	ON-LINE FAULT TOLERANT OPERATION VIA INCREMENTAL RECONFIGURATION OF FIELD PROGRAMMABLE GATE ARRAYS

22

Patent #:	6380759	Issue Dt:	04/30/2002	Application #:	09626094	Filing Dt:	07/26/2000
Title:	VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS

23

Patent #:	6567969	Issue Dt:	05/20/2003	Application #:	09632319	Filing Dt:	08/04/2000
Title:	CONFIGURABLE LOGIC ARRAY INCUDING LOOKUP TABLE MEANS FOR GENERATING FUNCTIONS OF DIFFERENT NUMBERS OF INPUT TERMS

24

Patent #:	6627947	Issue Dt:	09/30/2003	Application #:	09643279	Filing Dt:	08/22/2000
Title:	COMPACT SINGLE-POLY TWO-TRANSISTOR EEPROM CELL

25

Patent #:	6433602	Issue Dt:	08/13/2002	Application #:	09651689	Filing Dt:	08/30/2000
Title:	HIGH SPEED SCHMITT TRIGGER WITH LOW SUPPLY VOLTAGE

26

Patent #:	6455912	Issue Dt:	09/24/2002	Application #:	09651805	Filing Dt:	11/09/2000
Title:	PROCESS FOR MANUFACTURING SHALLOW TRENCHES FILLED WITH DIELECTRIC MATERIAL HAVING LOW MECHANICAL STRESS

27

Patent #:	6370071	Issue Dt:	04/09/2002	Application #:	09660707	Filing Dt:	09/13/2000
Title:	High voltage CMOS switch

28

Patent #:	6462576	Issue Dt:	10/08/2002	Application #:	09661585	Filing Dt:	09/14/2000
Title:	PROGRAMMABLE LOGIC DEVICE

29

Patent #:	6701340	Issue Dt:	03/02/2004	Application #:	09668896	Filing Dt:	09/22/2000
Title:	DOUBLE DIFFERENTIAL COMPARATOR AND PROGRAMMABLE ANALOG BLOCK ARCHITECTURE USING SAME

30

Patent #:	6249144	Issue Dt:	06/19/2001	Application #:	09669186	Filing Dt:	09/25/2000
Title:	Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources

31

Patent #:	6631487	Issue Dt:	10/07/2003	Application #:	09671853	Filing Dt:	09/27/2000
Title:	ON-LINE TESTING OF FIELD PROGRAMMABLE GATE ARRAY RESOURCES

32

Patent #:	6470485	Issue Dt:	10/22/2002	Application #:	09692694	Filing Dt:	10/18/2000
Title:	SCALABLE AND PARALLEL PROCESSING METHODS AND STRUCTURES FOR TESTING CONFIGURABLE INTERCONNECT NETWORK IN FPGA DEVICE

33

Patent #:	6507212	Issue Dt:	01/14/2003	Application #:	09704487	Filing Dt:	11/02/2000
Title:	WIDE INPUT PROGRAMMABLE LOGIC SYSTEM AND METHOD

34

Patent #:	6356107	Issue Dt:	03/12/2002	Application #:	09712000	Filing Dt:	11/13/2000
Title:	Method and structure dynamic in-system programming

35

Patent #:	6348813	Issue Dt:	02/19/2002	Application #:	09721153	Filing Dt:	11/22/2000
Title:	Scalable architecture for high density cPLD's having two-level hierarchy of routing resources

36

Patent #:	6524911	Issue Dt:	02/25/2003	Application #:	09731184	Filing Dt:	12/07/2000
Publication #:	US20030036230	Pub Dt:	02/20/2003
Title:	COMBINATION OF BPTEOS OXIDE FILM WITH CMP AND RTA TO ACHIEVE GOOD DATA RETENTION

37

Patent #:	6287916	Issue Dt:	09/11/2001	Application #:	09731185	Filing Dt:	12/07/2000
Title:	METHOD FOR FORMING A SEMICONDUCTOR DEVICE USING LPCVD NITRIDE TO PROTECT FLOATING GATE FROM CHARGE LOSS

38

Patent #:	6735706	Issue Dt:	05/11/2004	Application #:	09732216	Filing Dt:	12/06/2000
Publication #:	US20020104031	Pub Dt:	08/01/2002
Title:	PROGRAMMABLE POWER MANAGEMENT SYSTEM AND METHOD

39

Patent #:	6526558	Issue Dt:	02/25/2003	Application #:	09733878	Filing Dt:	12/08/2000
Publication #:	US20010056570	Pub Dt:	12/27/2001
Title:	METHODS FOR CONFIGURING FPGA'S HAVING VARIABLE GRAIN BLOCKS AND SHARED LOGIC FOR PROVIDING SYMMETRIC ROUTING OF RESULT OUTPUT TO DIFFERENTLY-DIRECTED AND TRISTATEABLE INTERCONNECT RESOURCES

40

Patent #:	6462602	Issue Dt:	10/08/2002	Application #:	09775488	Filing Dt:	02/01/2001
Publication #:	US20020101274	Pub Dt:	08/01/2002
Title:	VOLTAGE LEVEL TRANSLATOR SYSTEMS AND METHODS

41

Patent #:	6414521	Issue Dt:	07/02/2002	Application #:	09775489	Filing Dt:	02/01/2001
Title:	SENSE AMPLIFIER SYSTEMS AND METHODS

42

Patent #:	6496969	Issue Dt:	12/17/2002	Application #:	09818257	Filing Dt:	03/27/2001
Publication #:	US20020174411	Pub Dt:	11/21/2002
Title:	PROGRAMMING PROGRAMMABLE LOGIC DEVICES USING HIDDEN SWITCHES

43

Patent #:	6590415	Issue Dt:	07/08/2003	Application #:	09841209	Filing Dt:	04/23/2001
Publication #:	US20020196809	Pub Dt:	12/26/2002
Title:	METHODS FOR CONFIGURING FPGA ' S HAVING VARIABLE GRAIN COMPONENTS FOR PROVIDING TIME-SHARED ACCESS TO INTERCONNECT RESOURCES

44

Patent #:	6535043	Issue Dt:	03/18/2003	Application #:	09863656	Filing Dt:	05/23/2001
Publication #:	US20010055357	Pub Dt:	12/27/2001
Title:	CLOCK SIGNAL SELECTION SYSTEM, METHOD OF GENERATING A CLOCK SIGNAL AND PROGRAMMABLE CLOCK MANAGER INCLUDING SAME

45

Patent #:	6486705	Issue Dt:	11/26/2002	Application #:	09864276	Filing Dt:	05/25/2001
Publication #:	US20020003445	Pub Dt:	01/10/2002
Title:	SIGNAL DISTRIBUTION SCHEME IN FIELD PROGRAMMABLE GATE ARRAY (FPGA) OR FIELD PROGRAMMABLE SYSTEM CHIP (FPSC) INCLUDING CYCLE STEALING UNITS

46

Patent #:	6483342	Issue Dt:	11/19/2002	Application #:	09864277	Filing Dt:	05/25/2001
Publication #:	US20020008540	Pub Dt:	01/24/2002
Title:	MULTI-MASTER MULTI-SLAVE SYSTEM BUS IN A FIELD PROGRAMMABLE GATE ARRAY (FPGA)

47

Patent #:	6472904	Issue Dt:	10/29/2002	Application #:	09864284	Filing Dt:	05/25/2001
Publication #:	US20020003436	Pub Dt:	01/10/2002
Title:	DOUBLE DATA RATE INPUT AND OUTPUT IN A PROGRAMMABLE LOGIC DEVICE

48

Patent #:	6480026	Issue Dt:	11/12/2002	Application #:	09864289	Filing Dt:	05/25/2001
Publication #:	US20020003435	Pub Dt:	01/10/2002
Title:	MULTI-FUNCTIONAL I/O BUFFERS IN A FIELD PROGRAMMABLE GATE ARRAY (FPGA)

49

Patent #:	6772230	Issue Dt:	08/03/2004	Application #:	09864290	Filing Dt:	05/25/2001
Publication #:	US20020010902	Pub Dt:	01/24/2002
Title:	FIELD PROGRAMMABLE GATE ARRAY (FPGA) BIT STREAM FORMAT

50

Patent #:	6455375	Issue Dt:	09/24/2002	Application #:	09870541	Filing Dt:	06/01/2001
Title:	EEPROM TUNNEL WINDOW FOR PROGRAM INJECTION VIA P+ CONTACTED INVERSION

51

Patent #:	6498538	Issue Dt:	12/24/2002	Application #:	09870877	Filing Dt:	05/30/2001
Title:	LOW JITTER INTEGRATED PHASE LOCKED LOOP WITH BROAD TUNING RANGE

52

Patent #:	6614291	Issue Dt:	09/02/2003	Application #:	09881950	Filing Dt:	06/15/2001
Title:	LOW VOLTAGE, HIGH SPEED CMOS CML LATCH AND MUX DEVICES

53

Patent #:	6429692	Issue Dt:	08/06/2002	Application #:	09885243	Filing Dt:	06/19/2001
Title:	HIGH SPEED DATA SAMPLING WITH REDUCED METASTABILITY

54

Patent #:	6492877	Issue Dt:	12/10/2002	Application #:	09927289	Filing Dt:	08/09/2001
Title:	COUPLING FOR LC-BASED VCO

55

Patent #:	6525617	Issue Dt:	02/25/2003	Application #:	09927612	Filing Dt:	08/09/2001
Title:	BUFFERING FOR LC-BASED STAGE

56

Patent #:	6653860	Issue Dt:	11/25/2003	Application #:	09927793	Filing Dt:	08/10/2001
Publication #:	US20030107401	Pub Dt:	06/12/2003
Title:	ENHANCED MACROCELL MODULE HAVING EXPANDABLE PRODUCT TERM SHARING CAPABILITY FOR USE IN HIGH DENSITY CPLD ARCHITECTURES

Assignors

1

LATTICE SEMICONDUCTOR CORPORATION

Exec Dt:

03/10/2015

2

Exec Dt:

03/10/2015

3

SILICON IMAGE, INC.

Exec Dt:

03/10/2015

4

Exec Dt:

03/10/2015

Assignee

1

JEFFERIES FINANCE LLC

520 MADISON AVENUE

NEW YORK, NEW YORK 10022

Correspondence name and address
	PROSKAUER ROSE LLP
	ONE INTERNATIONAL PLACE
	BOSTON, MA 02110

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