|
Total properties:
30
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1993
|
Application #:
|
07869683
|
Filing Dt:
|
04/15/1992
|
|
Title:
|
DYNAMIC RANDOM ACCESS MEMORY CELL HAVING A STACKED-TRENCH CAPACITOR THAT IS RESISTANT TO ALPHA PARTICLE GENERATED SOFT ERRORS, AND METHOD OF MANUFACTURING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/1997
|
Application #:
|
08509782
|
Filing Dt:
|
08/01/1995
|
|
Title:
|
SEMICONDUCTOR PROCESSING METHOD OF FORMING FIELD OXIDE REGIONS ON A SEMICONDUCTOR SUBSTRATE UTILIZING A LATERALLY OUTWARD PROJECTING FOOT PORTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/1997
|
Application #:
|
08514159
|
Filing Dt:
|
08/11/1995
|
|
Title:
|
METHOD FOR FORMING FIELD OXIDE HAVING UNIFORM THICKNESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1998
|
Application #:
|
08539855
|
Filing Dt:
|
10/06/1995
|
|
Title:
|
INTEGRATED CHIP MULTILAYER DECOUPLING CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/1997
|
Application #:
|
08590313
|
Filing Dt:
|
01/23/1996
|
|
Title:
|
METHOD FOR LOCAL OXIDATION OF SILICON (LOCOS)FIELD ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08604219
|
Filing Dt:
|
02/20/1996
|
|
Title:
|
INTEGRATED CIRCUIT DEVICE HAVING CYANATE ESTER BUFFER COAT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/1998
|
Application #:
|
08607801
|
Filing Dt:
|
02/27/1996
|
|
Title:
|
MODIFIED LOCOS PROCESS FOR SUB-HALF-MICRON TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/1999
|
Application #:
|
08710370
|
Filing Dt:
|
09/16/1996
|
|
Title:
|
METHOD FOR ELECTROCHEMICAL LOCAL OXIDATION OF SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08723263
|
Filing Dt:
|
09/30/1996
|
|
Title:
|
REDUCED RC DELAY BETWEEN ADJACENT SUBSTRATE WIRING LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/1998
|
Application #:
|
08724319
|
Filing Dt:
|
10/01/1996
|
|
Title:
|
REDUCED RC DELAY BETWEEN ADJACENT SUBSTRATE WIRING LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/1999
|
Application #:
|
08801811
|
Filing Dt:
|
02/14/1997
|
|
Title:
|
METHOD MAKING INTRGRATED CIRCUIT METALLIZATION WITH SUPERCONDUCTOR BEOL WIRING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/1998
|
Application #:
|
08802164
|
Filing Dt:
|
02/13/1997
|
|
Title:
|
NMOS FIELD EFFECT TRANSISTORS AND METHODS OF FORMING NMOS FIELD EFFECT TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2000
|
Application #:
|
08902763
|
Filing Dt:
|
07/30/1997
|
|
Title:
|
NMOS FIELD EFFECT TRANSISTORS AND METHODS OF FORMING NMOS FIELD EFFECT TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
08906409
|
Filing Dt:
|
08/05/1997
|
|
Title:
|
METHOD FOR LOCAL OXIDATION OF SILICON (LOCOS) FIELD ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2000
|
Application #:
|
08919849
|
Filing Dt:
|
08/28/1997
|
|
Title:
|
INTEGRATED CHIP MULTILAYER DECOUPLING CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
08931093
|
Filing Dt:
|
08/20/1997
|
|
Title:
|
ASSISTED LOCAL OXIDATION OF SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2000
|
Application #:
|
08953910
|
Filing Dt:
|
10/20/1997
|
|
Title:
|
METHODS OF FORMING CONDUCTIVE COMPONENTS AND METHODS OF FORMING CONDUCTIVE LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
09024234
|
Filing Dt:
|
02/17/1998
|
|
Title:
|
INTEGRATED CIRCUIT METALLIZATION WITH SUPERCONDUCTOR BEOL WIRING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09145107
|
Filing Dt:
|
09/02/1998
|
|
Title:
|
VARIABLE TEMPERATURE LOCOS PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09207890
|
Filing Dt:
|
12/08/1998
|
|
Title:
|
REDUCED RC DELAY BETWEEN ADJACENT SUBSTRATE WIRING LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09245999
|
Filing Dt:
|
02/05/1999
|
|
Title:
|
METHOD FOR ELECTROCHEMICAL OXIDATION OF SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
09257402
|
Filing Dt:
|
02/25/1999
|
|
Title:
|
METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICE HAVING CYANATE ESTER BUFFER COAT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09385698
|
Filing Dt:
|
08/30/1999
|
|
Title:
|
METHOD OF FORMING FIELD OXIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09387661
|
Filing Dt:
|
08/30/1999
|
|
Title:
|
LOCOS PROCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09459131
|
Filing Dt:
|
12/10/1999
|
|
Title:
|
INTEGRATED CHIP MULTIPLAYER DECOUPLING CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09515519
|
Filing Dt:
|
02/29/2000
|
|
Title:
|
Reduced rc delay between adjacent substrate wiring lines
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2002
|
Application #:
|
09552738
|
Filing Dt:
|
04/19/2000
|
|
Title:
|
METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICE HAVING CYANATE ESTER BUFFER COAT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09560704
|
Filing Dt:
|
04/27/2000
|
|
Title:
|
LOCOS fabrication processes and semiconductive material structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
10156515
|
Filing Dt:
|
05/28/2002
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2002
| | | | |
|
Title:
|
REDUCED RC DELAY BETWEEN ADJACENT SUBSTRATE WIRING LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
10196458
|
Filing Dt:
|
07/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
INTEGRATED CIRCUIT DEVICE HAVING CYANATE ESTER BUFFER COAT AND METHOD OF FABRICATING SAME
|
|
