Total properties:
727
Page
5
of
8
Pages:
1 2 3 4 5 6 7 8
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13026168
|
Filing Dt:
|
02/11/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
|
Title:
|
POLY-OXYCARBOSILANE COMPOSITIONS FOR USE IN IMPRINT LITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13031754
|
Filing Dt:
|
02/22/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
|
Title:
|
METHOD, SYSTEM, AND DESIGN STRUCTURE FOR MAKING VOLTAGE ENVIRONMENT CONSISTENT FOR REUSED SUB MODULES IN CHIP DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13041248
|
Filing Dt:
|
03/04/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING AN IMPROVED STORE-IN CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13050519
|
Filing Dt:
|
03/17/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
|
Title:
|
POLYMERIC MATERIAL, METHOD OF FORMING THE POLYMERIC MATERIAL, AND MEHTOD OF FORMING A THIN FILM USING THE POLYMERIC MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13052956
|
Filing Dt:
|
03/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
|
Title:
|
METHOD OF MANUFACTURING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
13075552
|
Filing Dt:
|
03/30/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
|
Title:
|
SOI BODY CONTACT USING E-DRAM TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13076192
|
Filing Dt:
|
03/30/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR MANUFACTURING ELECTRONIC INTEGRATED CIRCUIT CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13077216
|
Filing Dt:
|
03/31/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2011
| | | | |
|
Title:
|
METHOD OF PLACING A SEMICONDUCTING NANOSTRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTING NANOSTRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13078305
|
Filing Dt:
|
04/01/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
|
Title:
|
MULTILAYERED LOW K CAP WITH CONFORMAL GAP FILL AND UV STABLE COMPRESSIVE STRESS PROPERTIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13079842
|
Filing Dt:
|
04/05/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2012
| | | | |
|
Title:
|
Dynamically Tune Power Proxy Architectures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13080773
|
Filing Dt:
|
04/06/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2011
| | | | |
|
Title:
|
PROCESSING EXECUTION REQUESTS WITHIN DIFFERENT COMPUTING ENVIRONMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13093034
|
Filing Dt:
|
04/25/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/11/2011
| | | | |
|
Title:
|
SILICON-ON-INSULATOR SUBSTRATE WITH BUILT-IN SUBSTRATE JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13095969
|
Filing Dt:
|
04/28/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
|
Title:
|
SILICON CHICKLET PEDESTAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13095973
|
Filing Dt:
|
04/28/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
|
Title:
|
SILICON CHICKLET PEDESTAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13097307
|
Filing Dt:
|
04/29/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
|
Title:
|
METHOD FOR FABRICATION OF CRYSTALLINE DIODES FOR RESISTIVE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13103197
|
Filing Dt:
|
05/09/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2011
| | | | |
|
Title:
|
METAL-GATE HIGH-K REFERENCE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13107515
|
Filing Dt:
|
05/13/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/08/2011
| | | | |
|
Title:
|
TECHNIQUE FOR ENHANCING TRANSISTOR PERFORMANCE BY TRANSISTOR SPECIFIC CONTACT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
13116396
|
Filing Dt:
|
05/26/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
|
Title:
|
SOI RADIO FREQUENCY SWITCH WITH ENHANCED SIGNAL FIDELITY AND ELECTRICAL ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13116416
|
Filing Dt:
|
05/26/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
|
Title:
|
CHARGE BREAKDOWN AVOIDANCE FOR MIM ELEMENTS IN SOI BASE TECHNOLOGY AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13135031
|
Filing Dt:
|
06/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
01/05/2012
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR SELECTIVE EPITAXY OF SI-CONTAINING MATERIALS AND SUBSTITUTIONALLY DOPED CRYSTALLINE SI-CONTAINING MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13164899
|
Filing Dt:
|
06/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2012
| | | | |
|
Title:
|
METHOD OF CONTROLLING CRITICAL DIMENSIONS OF VIAS IN A METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE DURING SILICON-ARC ETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
13167303
|
Filing Dt:
|
06/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
|
Title:
|
STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13174841
|
Filing Dt:
|
07/01/2011
|
|
Publication #:
|
|
Pub Dt:
|
10/27/2011
| | | | |
|
Title:
|
HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13178587
|
Filing Dt:
|
07/08/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2012
| | | | |
|
Title:
|
RE-ESTABLISHING SURFACE CHARACTERISTICS OF SENSITIVE LOW-K DIELECTRICS IN MICROSTRUCTURE DEVICES BY USING AN IN SITU SURFACE MODIFICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13183549
|
Filing Dt:
|
07/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2012
| | | | |
|
Title:
|
OXIDE DEPOSITION BY USING A DOUBLE LINER APPROACH FOR REDUCING PATTERN DENSITY DEPENDENCE IN SOPHISTICATED SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13185055
|
Filing Dt:
|
07/18/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
|
Title:
|
VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13187076
|
Filing Dt:
|
07/20/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2012
| | | | |
|
Title:
|
SUBSTRATE DICING TECHNIQUE FOR SEPARATING SEMICONDUCTOR DIES WITH REDUCED AREA CONSUMPTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13195155
|
Filing Dt:
|
08/01/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
|
Title:
|
SCALING OF BIPOLAR TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13198107
|
Filing Dt:
|
08/04/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
|
Title:
|
HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY CAP LAYER REMOVAL WITHOUT SACRIFICIAL SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2016
|
Application #:
|
13219144
|
Filing Dt:
|
08/26/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
|
Title:
|
PATTERNABLE DIELECTRIC FILM STRUCTURE WITH IMPROVED LITHOGRAPHY AND METHOD OF FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13219331
|
Filing Dt:
|
08/26/2011
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
|
Title:
|
FABRICATION OF A SEMICONDUCTOR DEVICE WITH EXTENDED EPITAXIAL SEMICONDUCTOR REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13220753
|
Filing Dt:
|
08/30/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
|
Title:
|
STRAIN-COMPENSATED FIELD EFFECT TRANSISTOR AND ASSOCIATED METHOD OF FORMING THE TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13226681
|
Filing Dt:
|
09/07/2011
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
|
Title:
|
MULTIPATH SOLDERED THERMAL INTERFACE BETWEEN A CHIP AND ITS HEAT SINK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13229250
|
Filing Dt:
|
09/09/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
|
Title:
|
MECHANICALLY ROBUST METAL/LOW-k INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13233064
|
Filing Dt:
|
09/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT STRUCTURE HAVING SELECTIVELY FORMED METAL CAP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13237386
|
Filing Dt:
|
09/20/2011
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
|
Title:
|
METHOD OF CONCETRATING SOLAR ENERGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
13252152
|
Filing Dt:
|
10/03/2011
|
|
Publication #:
|
|
Pub Dt:
|
01/26/2012
| | | | |
|
Title:
|
POLYSILICON PLUG BIPOLAR TRANSISTOR FOR PHASE CHANGE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13252424
|
Filing Dt:
|
10/04/2011
|
|
Publication #:
|
|
Pub Dt:
|
01/26/2012
| | | | |
|
Title:
|
NOVEL REWORKABLE UNDERFILLS FOR CERAMIC MCM C4 PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13278552
|
Filing Dt:
|
10/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
|
Title:
|
CARBON NANOTUBE TRANSISTOR EMPLOYING EMBEDDED ELECTRODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13280853
|
Filing Dt:
|
10/25/2011
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2012
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR TRACKING UNCERTAIN SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13281688
|
Filing Dt:
|
10/26/2011
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
|
Title:
|
HIGH SELECTIVITY NITRIDE ETCH PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13281715
|
Filing Dt:
|
10/26/2011
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
|
Title:
|
HIGH ASPECT RATIO AND REDUCED UNDERCUT TRENCH ETCH PROCESS FOR A SEMICONDUCTOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13283819
|
Filing Dt:
|
10/28/2011
|
|
Publication #:
|
|
Pub Dt:
|
02/16/2012
| | | | |
|
Title:
|
METHODS FOR ENHANCING QUALITY OF PIXEL SENSOR IMAGE FRAMES FOR GLOBAL SHUTTER IMAGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13296444
|
Filing Dt:
|
11/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
|
Title:
|
PROCESS TO REMOVE NI AND PT RESIDUES FOR NIPTSI APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13301841
|
Filing Dt:
|
11/22/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/22/2012
| | | | |
|
Title:
|
SELF-FORMING TOP ANTI-REFLECTIVE COATING COMPOSITIONS AND, PHOTORESIST MIXTURES AND METHOD OF IMAGING USING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13326404
|
Filing Dt:
|
12/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
04/05/2012
| | | | |
|
Title:
|
METHOD FOR USING A TOPCOAT COMPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
13346043
|
Filing Dt:
|
01/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
|
Title:
|
IN SITU DOPING AND DIFFUSIONLESS ANNEALING OF EMBEDDED STRESSOR REGIONS IN PMOS AND NMOS DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13348101
|
Filing Dt:
|
01/11/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
|
Title:
|
METHOD OF FORMING TRANSISTOR WITH INCREASED GATE WIDTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13349883
|
Filing Dt:
|
01/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
|
Title:
|
FABRICATION OF SEMICONDUCTORS WITH HIGH-K/METAL GATE ELECTRODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13354715
|
Filing Dt:
|
01/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
|
Title:
|
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13354883
|
Filing Dt:
|
01/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
|
Title:
|
METHOD FOR AUTOMATIC GENERATION OF THROUGHPUT MODELS FOR SEMICONDUCTOR TOOLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13355065
|
Filing Dt:
|
01/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
|
Title:
|
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13355099
|
Filing Dt:
|
01/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
|
Title:
|
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13359032
|
Filing Dt:
|
01/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
|
Title:
|
METHOD OF FORMING MIM CAPACITOR STRUCTURE IN FEOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
13363944
|
Filing Dt:
|
02/01/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
RECESSED GATE CHANNEL WITH LOW VT CORNER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13364759
|
Filing Dt:
|
02/02/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
|
Title:
|
METHOD AND STRUCTURE FOR ULTRA-HIGH DENSITY, HIGH DATA RATE FERROELECTRIC STORAGE DISK TECHNOLOGY USING STABILIZATION BY A SURFACE CONDUCTING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13365577
|
Filing Dt:
|
02/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
|
Title:
|
NANOFLUIDIC FIELD EFFECT TRANSISTOR BASED ON SURFACE CHARGE MODULATED NANOCHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13370898
|
Filing Dt:
|
02/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
|
Title:
|
STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13396998
|
Filing Dt:
|
02/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
|
Title:
|
Template-Registered DiBlock Copolymer Mask for MRAM Device Formation
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13398481
|
Filing Dt:
|
02/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
|
Title:
|
3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13398505
|
Filing Dt:
|
02/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2012
| | | | |
|
Title:
|
3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13400900
|
Filing Dt:
|
02/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
|
Title:
|
REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13406956
|
Filing Dt:
|
02/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2012
| | | | |
|
Title:
|
PRECISION PEAK MATCHING IN LIQUID CHROMATOGRAPHY-MASS SPECTROSCOPY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13414954
|
Filing Dt:
|
03/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
|
ASYMMETRIC COMPLEMENTARY DIPOLE ILLUMINATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13415106
|
Filing Dt:
|
03/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
|
ASYMMETRIC COMPLEMENTARY DIPOLE ILLUMINATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13415372
|
Filing Dt:
|
03/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
|
METAL DENSITY AWARE SIGNAL ROUTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13417879
|
Filing Dt:
|
03/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
|
Continuously Referencing Signals Over Multiple Layers in Laminate Packages
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13419624
|
Filing Dt:
|
03/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
|
METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13423716
|
Filing Dt:
|
03/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
|
Title:
|
STRESSED SOURCE/DRAIN CMOS AND METHOD FOR FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13423838
|
Filing Dt:
|
03/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
|
Title:
|
ORGANIC GRADED SPIN ON BARC COMPOSITIONS FOR HIGH NA LITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13425681
|
Filing Dt:
|
03/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
BULK SUBSTRATE FET INTEGRATED ON CMOS SOI
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
|
13426892
|
Filing Dt:
|
03/22/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
|
Title:
|
REDUCING IMPEDANCE DISCONTINUITY IN PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13429981
|
Filing Dt:
|
03/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
|
Title:
|
THREAD SERIALIZATION AND DISABLEMENT TOOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13431254
|
Filing Dt:
|
03/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13431328
|
Filing Dt:
|
03/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
|
Title:
|
METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SIGE CHANNEL ENGINEERING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13432716
|
Filing Dt:
|
03/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13432963
|
Filing Dt:
|
03/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
FORMING SEMICONDUCTOR CHIP CONNECTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13432966
|
Filing Dt:
|
03/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
REMOVING MATERIAL FROM DEFECTIVE OPENING IN GLASS MOLD AND RELATED GLASS MOLD FOR INJECTION MOLDED SOLDER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13438230
|
Filing Dt:
|
04/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13442087
|
Filing Dt:
|
04/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
|
Title:
|
HIGH-K TRANSISTORS WITH LOW THRESHOLD VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13442090
|
Filing Dt:
|
04/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
|
Title:
|
HIGH-K TRANSISTORS WITH LOW THRESHOLD VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13443427
|
Filing Dt:
|
04/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR SUB-PELLICLE DEFECT REDUCTION ON PHOTOMASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13444193
|
Filing Dt:
|
04/11/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
|
Title:
|
ELECTROSTATIC CHUCKING OF AN INSULATOR HANDLE SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13445194
|
Filing Dt:
|
04/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
|
Title:
|
PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13453165
|
Filing Dt:
|
04/23/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
|
Title:
|
STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13453262
|
Filing Dt:
|
04/23/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
|
Title:
|
FRACTURING CONTINUOUS PHOTOLITHOGRAPHY MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13455616
|
Filing Dt:
|
04/25/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
|
Title:
|
METHODS OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE FORMED USING REPLACEMENT GATE TECHNIQUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13463879
|
Filing Dt:
|
05/04/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
|
Title:
|
NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13466895
|
Filing Dt:
|
05/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/14/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUITS AND PROCESSES FOR FORMING INTEGRATED CIRCUITS HAVING AN EMBEDDED ELECTRICAL INTERCONNECT WITHIN A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13468083
|
Filing Dt:
|
05/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13468270
|
Filing Dt:
|
05/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
|
Title:
|
Structure and Method for Manufacturing Asymmetric Devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13469487
|
Filing Dt:
|
05/11/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
|
Title:
|
ELECTRONIC DEVICE WITH AEROGEL THERMAL ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13471627
|
Filing Dt:
|
05/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
|
Title:
|
SYSTEM AND METHOD TO IMPROVE CHIP YIELD, RELIABILITY AND PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13474090
|
Filing Dt:
|
05/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
WAFER DICING EMPLOYING EDGE REGION UNDERFILL REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13474790
|
Filing Dt:
|
05/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
|
Title:
|
TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13475503
|
Filing Dt:
|
05/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
LOW TEMPERATURE SELECTIVE EPITAXY OF SILICON GERMANIUM ALLOYS EMPLOYING CYCLIC DEPOSIT AND ETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13476692
|
Filing Dt:
|
05/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/21/2013
| | | | |
|
Title:
|
METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES BY FORMING A COPPER-BASED SEED LAYER HAVING AN AS-DEPOSITED THICKNESS PROFILE AND THEREAFTER PERFORMING AN ETCHING PROCESS AND ELECTROLESS COPPER DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13476860
|
Filing Dt:
|
05/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/21/2013
| | | | |
|
Title:
|
METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS PROFILE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13489244
|
Filing Dt:
|
06/05/2012
|
|
Title:
|
AQUA REGIA AND HYDROGEN PEROXIDE HCL COMBINATION TO REMOVE NI AND NIPT RESIDUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13490840
|
Filing Dt:
|
06/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUITS HAVING A CONTINUOUS ACTIVE AREA AND METHODS FOR FABRICATING SAME
|
|
