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Reel/Frame:	054479/0842			Pages:	121
		Recorded:	11/19/2020
Attorney Dkt #:	0941-4477M
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 727
Page 7 of 8
Pages: 1 2 3 4 5 6 7 8

Patent #:	8828521	Issue Dt:	09/09/2014	Application #:	13912593	Filing Dt:	06/07/2013
Publication #:	US20130273325	Pub Dt:	10/17/2013
Title:	CORRUGATED INTERFACES FOR MULTILAYERED INTERCONNECTS

Patent #:	9006705	Issue Dt:	04/14/2015	Application #:	13914514	Filing Dt:	06/10/2013
Publication #:	US20140054547	Pub Dt:	02/27/2014
Title:	DEVICE WITH STRAINED LAYER FOR QUANTUM WELL CONFINEMENT AND METHOD FOR MANUFACTURING THEREOF

Patent #:	8819860	Issue Dt:	08/26/2014	Application #:	13920676	Filing Dt:	06/18/2013
Publication #:	US20130278363	Pub Dt:	10/24/2013
Title:	DEVICE COMPRISING A CANTILEVER AND SCANNING SYSTEM

Patent #:	8648647	Issue Dt:	02/11/2014	Application #:	13922854	Filing Dt:	06/20/2013
Publication #:	US20130278281	Pub Dt:	10/24/2013
Title:	DETERMINING CURRENT OF A FIRST FET OF BODY CONNECTED FETS

Patent #:	8673760	Issue Dt:	03/18/2014	Application #:	13925200	Filing Dt:	06/24/2013
Title:	METHODS OF FORMING STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT

Patent #:	9064702	Issue Dt:	06/23/2015	Application #:	13956273	Filing Dt:	07/31/2013
Publication #:	US20140038426	Pub Dt:	02/06/2014
Title:	METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

Patent #:	8906794	Issue Dt:	12/09/2014	Application #:	13956844	Filing Dt:	08/01/2013
Title:	GATE SILICIDATION

Patent #:	9917087	Issue Dt:	03/13/2018	Application #:	13961554	Filing Dt:	08/07/2013
Publication #:	US20150041910	Pub Dt:	02/12/2015
Title:	INTEGRATED CIRCUITS WITH A PARTIALLY-DEPLETED REGION FORMED OVER A BULK SILICON SUBSTRATE AND METHODS FOR FABRICATING THE SAME

Patent #:	9166023	Issue Dt:	10/20/2015	Application #:	13964009	Filing Dt:	08/09/2013
Publication #:	US20150041898	Pub Dt:	02/12/2015
Title:	BULK FINFET SEMICONDUCTOR-ON-NOTHING INTEGRATION

Patent #:	9343354	Issue Dt:	05/17/2016	Application #:	13970124	Filing Dt:	08/19/2013
Publication #:	US20130330923	Pub Dt:	12/12/2013
Title:	MIDDLE OF LINE STRUCTURES AND METHODS FOR FABRICATION

Patent #:	9287345	Issue Dt:	03/15/2016	Application #:	14013409	Filing Dt:	08/29/2013
Publication #:	US20140001599	Pub Dt:	01/02/2014
Title:	SEMICONDUCTOR STRUCTURE WITH THIN FILM RESISTOR AND TERMINAL BOND PAD

Patent #:	8828826	Issue Dt:	09/09/2014	Application #:	14015531	Filing Dt:	08/30/2013
Publication #:	US20140061735	Pub Dt:	03/06/2014
Title:	A METHOD FOR MANUFACTURING A TRANSISTOR DEVICE COMPRISING A GERMANIUM BASED CHANNEL LAYER

Patent #:	8963225	Issue Dt:	02/24/2015	Application #:	14024820	Filing Dt:	09/12/2013
Publication #:	US20140077332	Pub Dt:	03/20/2014
Title:	Band Engineered Semiconductor Device and Method for Manufacturing Thereof

Patent #:	8878300	Issue Dt:	11/04/2014	Application #:	14030048	Filing Dt:	09/18/2013
Title:	SEMICONDUCTOR DEVICE INCLUDING OUTWARDLY EXTENDING SOURCE AND DRAIN SILICIDE CONTACT REGIONS AND RELATED METHODS

Patent #:	9776270	Issue Dt:	10/03/2017	Application #:	14043047	Filing Dt:	10/01/2013
Publication #:	US20150089805	Pub Dt:	04/02/2015
Title:	CHIP JOINING BY INDUCTION HEATING

Patent #:	8722470	Issue Dt:	05/13/2014	Application #:	14046316	Filing Dt:	10/04/2013
Publication #:	US20140027058	Pub Dt:	01/30/2014
Title:	CMOS WITH CHANNEL P-FINFET AND CHANNEL N-FINFET HAVING DIFFERENT CRYSTALLINE ORIENTATIONS AND PARALLEL FINS

Patent #:	8723233	Issue Dt:	05/13/2014	Application #:	14046340	Filing Dt:	10/04/2013
Publication #:	US20140035008	Pub Dt:	02/06/2014
Title:	CMOS WITH CHANNEL P-FINFET AND CHANNEL N-FINFET HAVING DIFFERENT CRYSTALLINE ORIENTATIONS AND PARALLEL FINS

Patent #:	9633962	Issue Dt:	04/25/2017	Application #:	14048483	Filing Dt:	10/08/2013
Publication #:	US20150097283	Pub Dt:	04/09/2015
Title:	PLUG VIA FORMATION WITH GRID FEATURES IN THE PASSIVATION LAYER

Patent #:	8796771	Issue Dt:	08/05/2014	Application #:	14053708	Filing Dt:	10/15/2013
Publication #:	US20140042541	Pub Dt:	02/13/2014
Title:	CREATING ANISOTROPICALLY DIFFUSED JUNCTIONS IN FIELD EFFECT TRANSISTOR DEVICES

Patent #:	8803276	Issue Dt:	08/12/2014	Application #:	14073119	Filing Dt:	11/06/2013
Publication #:	US20140061803	Pub Dt:	03/06/2014
Title:	ELECTROSTATIC DISCHARGE (ESD) DEVICE AND METHOD OF FABRICATING

Patent #:	9064794	Issue Dt:	06/23/2015	Application #:	14073919	Filing Dt:	11/07/2013
Publication #:	US20140065787	Pub Dt:	03/06/2014
Title:	INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE

Patent #:	9006835	Issue Dt:	04/14/2015	Application #:	14074905	Filing Dt:	11/08/2013
Publication #:	US20140131805	Pub Dt:	05/15/2014
Title:	TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET AND SUPERIOR UNIFORMITY

Patent #:	9478489	Issue Dt:	10/25/2016	Application #:	14138881	Filing Dt:	12/23/2013
Publication #:	US20140110854	Pub Dt:	04/24/2014
Title:	SEMICONDUCTOR DIES WITH REDUCED AREA CONSUMPTION

Patent #:	9639652	Issue Dt:	05/02/2017	Application #:	14148234	Filing Dt:	01/06/2014
Publication #:	US20140123097	Pub Dt:	05/01/2014
Title:	COMPACT MODEL FOR DEVICE/CIRCUIT/CHIP LEAKAGE CURRENT (IDDQ) CALCULATION INCLUDING PROCESS INDUCED UPLIFT FACTORS

Patent #:	9478600	Issue Dt:	10/25/2016	Application #:	14175587	Filing Dt:	02/07/2014
Publication #:	US20140154849	Pub Dt:	06/05/2014
Title:	METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE

Patent #:	9392690	Issue Dt:	07/12/2016	Application #:	14177530	Filing Dt:	02/11/2014
Publication #:	US20140151097	Pub Dt:	06/05/2014
Title:	Method and Structure to Improve the Conductivity of Narrow Copper Filled Vias

Patent #:	8866257	Issue Dt:	10/21/2014	Application #:	14190514	Filing Dt:	02/26/2014
Publication #:	US20140177373	Pub Dt:	06/26/2014
Title:	SYSTEM INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES

Patent #:	9105718	Issue Dt:	08/11/2015	Application #:	14224384	Filing Dt:	03/25/2014
Publication #:	US20140203359	Pub Dt:	07/24/2014
Title:	BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION

Patent #:	9196475	Issue Dt:	11/24/2015	Application #:	14253906	Filing Dt:	04/16/2014
Publication #:	US20150303057	Pub Dt:	10/22/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FLUORINE INCORPORATION

Patent #:	9348216	Issue Dt:	05/24/2016	Application #:	14261687	Filing Dt:	04/25/2014
Publication #:	US20140234757	Pub Dt:	08/21/2014
Title:	TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS

Patent #:	9257557	Issue Dt:	02/09/2016	Application #:	14282463	Filing Dt:	05/20/2014
Publication #:	US20150340500	Pub Dt:	11/26/2015
Title:	SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS

Patent #:	9431540	Issue Dt:	08/30/2016	Application #:	14288766	Filing Dt:	05/28/2014
Publication #:	US20150349085	Pub Dt:	12/03/2015
Title:	METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SIDEWALL SPACERS FOR CONFINING EPITAXIAL GROWTH

Patent #:	9646838	Issue Dt:	05/09/2017	Application #:	14293627	Filing Dt:	06/02/2014
Publication #:	US20150031179	Pub Dt:	01/29/2015
Title:	METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING SILICIDED AND NON-SILICIDED CIRCUIT ELEMENTS

Patent #:	9406751	Issue Dt:	08/02/2016	Application #:	14296818	Filing Dt:	06/05/2014
Publication #:	US20150357243	Pub Dt:	12/10/2015
Title:	METHOD FOR MAKING STRAINED SEMICONDUCTOR DEVICE AND RELATED METHODS

Patent #:	9312142	Issue Dt:	04/12/2016	Application #:	14300705	Filing Dt:	06/10/2014
Publication #:	US20150357199	Pub Dt:	12/10/2015
Title:	CHEMICAL MECHANICAL POLISHING METHOD AND APPARATUS

Patent #:	9377251	Issue Dt:	06/28/2016	Application #:	14301623	Filing Dt:	06/11/2014
Publication #:	US20140290909	Pub Dt:	10/02/2014
Title:	THERMAL GROUND PLANE FOR COOLING A COMPUTER

Patent #:	9142640	Issue Dt:	09/22/2015	Application #:	14306864	Filing Dt:	06/17/2014
Title:	CONTAINMENT STRUCTURE FOR EPITAXIAL GROWTH IN NON-PLANAR SEMICONDUCTOR STRUCTURE

Patent #:	9391200	Issue Dt:	07/12/2016	Application #:	14308045	Filing Dt:	06/18/2014
Publication #:	US20150372140	Pub Dt:	12/24/2015
Title:	FINFETS HAVING STRAINED CHANNELS, AND METHODS OF FABRICATING FINFETS HAVING STRAINED CHANNELS

Patent #:	9613906	Issue Dt:	04/04/2017	Application #:	14311457	Filing Dt:	06/23/2014
Publication #:	US20150371898	Pub Dt:	12/24/2015
Title:	INTEGRATED CIRCUITS INCLUDING MODIFIED LINERS AND METHODS FOR FABRICATING THE SAME

Patent #:	9502518	Issue Dt:	11/22/2016	Application #:	14312418	Filing Dt:	06/23/2014
Publication #:	US20150372104	Pub Dt:	12/24/2015
Title:	MULTI-CHANNEL GATE-ALL-AROUND FET

Patent #:	9372392	Issue Dt:	06/21/2016	Application #:	14325515	Filing Dt:	07/08/2014
Publication #:	US20140329173	Pub Dt:	11/06/2014
Title:	RETICLES FOR USE IN FORMING IMPLANT MASKING LAYERS AND METHODS OF FORMING IMPLANT MASKING LAYERS

Patent #:	9058417	Issue Dt:	06/16/2015	Application #:	14457537	Filing Dt:	08/12/2014
Publication #:	US20140359583	Pub Dt:	12/04/2014
Title:	THREAD SERIALIZATION AND DISABLEMENT TOOL

Patent #:	9740092	Issue Dt:	08/22/2017	Application #:	14467489	Filing Dt:	08/25/2014
Publication #:	US20160055281	Pub Dt:	02/25/2016
Title:	MODEL-BASED GENERATION OF DUMMY FEATURES

Patent #:	9105722	Issue Dt:	08/11/2015	Application #:	14486108	Filing Dt:	09/15/2014
Publication #:	US20150001585	Pub Dt:	01/01/2015
Title:	TUCKED ACTIVE REGION WITHOUT DUMMY POLY FOR PERFORMANCE BOOST AND VARIATION REDUCTION

Patent #:	9379198	Issue Dt:	06/28/2016	Application #:	14494699	Filing Dt:	09/24/2014
Publication #:	US20150008527	Pub Dt:	01/08/2015
Title:	INTEGRATED CIRCUIT STRUCTURE HAVING SELECTIVELY FORMED METAL CAP

Patent #:	9263582	Issue Dt:	02/16/2016	Application #:	14502428	Filing Dt:	09/30/2014
Publication #:	US20150054083	Pub Dt:	02/26/2015
Title:	STRAIN ENGINEERING IN SEMICONDUCTOR DEVICES BY USING A PIEZOELECTRIC MATERIAL

Patent #:	10008597	Issue Dt:	06/26/2018	Application #:	14505536	Filing Dt:	10/03/2014
Publication #:	US20150054094	Pub Dt:	02/26/2015
Title:	SEMICONDUCTOR DEVICES WITH ASYMMETRIC HALO IMPLANTATION AND METHOD OF MANUFACTURE

Patent #:	9076810	Issue Dt:	07/07/2015	Application #:	14508011	Filing Dt:	10/07/2014
Publication #:	US20150024570	Pub Dt:	01/22/2015
Title:	SCALING OF BIPOLAR TRANSISTORS

Patent #:	9397174	Issue Dt:	07/19/2016	Application #:	14516623	Filing Dt:	10/17/2014
Publication #:	US20150035076	Pub Dt:	02/05/2015
Title:	Self-Aligned Gate Electrode Diffusion Barriers

Patent #:	9299665	Issue Dt:	03/29/2016	Application #:	14519235	Filing Dt:	10/21/2014
Publication #:	US20150171023	Pub Dt:	06/18/2015
Title:	FORMATION OF ALPHA PARTICLE SHIELDS IN CHIP PACKAGING

Patent #:	9640552	Issue Dt:	05/02/2017	Application #:	14519596	Filing Dt:	10/21/2014
Publication #:	US20150287809	Pub Dt:	10/08/2015
Title:	MULTI-HEIGHT FIN FIELD EFFECT TRANSISTORS

Patent #:	9349852	Issue Dt:	05/24/2016	Application #:	14520445	Filing Dt:	10/22/2014
Publication #:	US20150035059	Pub Dt:	02/05/2015
Title:	METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS

Patent #:	9847415	Issue Dt:	12/19/2017	Application #:	14523076	Filing Dt:	10/24/2014
Publication #:	US20150041896	Pub Dt:	02/12/2015
Title:	FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE

Patent #:	9583625	Issue Dt:	02/28/2017	Application #:	14523548	Filing Dt:	10/24/2014
Publication #:	US20160118500	Pub Dt:	04/28/2016
Title:	FIN STRUCTURES AND MULTI-VT SCHEME BASED ON TAPERED FIN AND METHOD TO FORM

Patent #:	9034746	Issue Dt:	05/19/2015	Application #:	14524023	Filing Dt:	10/27/2014
Publication #:	US20150044861	Pub Dt:	02/12/2015
Title:	GATE SILICIDATION

Patent #:	9660083	Issue Dt:	05/23/2017	Application #:	14560255	Filing Dt:	12/04/2014
Publication #:	US20160163850	Pub Dt:	06/09/2016
Title:	LDMOS FINFET DEVICE AND METHOD OF MANUFACTURE USING A TRENCH CONFINED EPITAXIAL GROWTH PROCESS

Patent #:	9685370	Issue Dt:	06/20/2017	Application #:	14574889	Filing Dt:	12/18/2014
Publication #:	US20160181151	Pub Dt:	06/23/2016
Title:	TITANIUM TUNGSTEN LINER USED WITH COPPER INTERCONNECTS

Patent #:	9601565	Issue Dt:	03/21/2017	Application #:	14578523	Filing Dt:	12/22/2014
Publication #:	US20160181359	Pub Dt:	06/23/2016
Title:	ZIG-ZAG TRENCH STRUCTURE TO PREVENT ASPECT RATIO TRAPPING DEFECT ESCAPE

Patent #:	10062762	Issue Dt:	08/28/2018	Application #:	14581857	Filing Dt:	12/23/2014
Publication #:	US20160181390	Pub Dt:	06/23/2016
Title:	SEMICONDUCTOR DEVICES HAVING LOW CONTACT RESISTANCE AND LOW CURRENT LEAKAGE

Patent #:	9515180	Issue Dt:	12/06/2016	Application #:	14588318	Filing Dt:	12/31/2014
Publication #:	US20160190314	Pub Dt:	06/30/2016
Title:	VERTICAL SLIT TRANSISTOR WITH OPTIMIZED AC PERFORMANCE

Patent #:	9029217	Issue Dt:	05/12/2015	Application #:	14592412	Filing Dt:	01/08/2015
Publication #:	US20150126010	Pub Dt:	05/07/2015
Title:	Band Engineered Semiconductor Device and Method for Manufacturing Thereof

Patent #:	9673083	Issue Dt:	06/06/2017	Application #:	14608729	Filing Dt:	01/29/2015
Publication #:	US20160225659	Pub Dt:	08/04/2016
Title:	METHODS OF FORMING FIN ISOLATION REGIONS ON FINFET SEMICONDUCTOR DEVICES BY IMPLANTATION OF AN OXIDATION-RETARDING MATERIAL

Patent #:	9373507	Issue Dt:	06/21/2016	Application #:	14618498	Filing Dt:	02/10/2015
Publication #:	US20150179453	Pub Dt:	06/25/2015
Title:	DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET

Patent #:	10192822	Issue Dt:	01/29/2019	Application #:	14623115	Filing Dt:	02/16/2015
Publication #:	US20160240478	Pub Dt:	08/18/2016
Title:	MODIFIED TUNGSTEN SILICON

Patent #:	9865564	Issue Dt:	01/09/2018	Application #:	14624601	Filing Dt:	02/18/2015
Publication #:	US20150162300	Pub Dt:	06/11/2015
Title:	LASER ASHING OF POLYIMIDE FOR SEMICONDUCTOR MANUFACTURING

Patent #:	10091909	Issue Dt:	10/02/2018	Application #:	14632180	Filing Dt:	02/26/2015
Publication #:	US20150195955	Pub Dt:	07/09/2015
Title:	METHOD AND DEVICE FOR COOLING A HEAT GENERATING COMPONENT

Patent #:	10278306	Issue Dt:	04/30/2019	Application #:	14632194	Filing Dt:	02/26/2015
Publication #:	US20150176911	Pub Dt:	06/25/2015
Title:	METHOD AND DEVICE FOR COOLING A HEAT GENERATING COMPONENT

Patent #:	10066303	Issue Dt:	09/04/2018	Application #:	14634535	Filing Dt:	02/27/2015
Publication #:	US20150247244	Pub Dt:	09/03/2015
Title:	THIN NIB OR COB CAPPING LAYER FOR NON-NOBLE METALLIC BONDING LANDING PADS

Patent #:	9633911	Issue Dt:	04/25/2017	Application #:	14668482	Filing Dt:	03/25/2015
Publication #:	US20150200205	Pub Dt:	07/16/2015
Title:	SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS

Patent #:	9653571	Issue Dt:	05/16/2017	Application #:	14739662	Filing Dt:	06/15/2015
Publication #:	US20160365425	Pub Dt:	12/15/2016
Title:	FREESTANDING SPACER HAVING SUB-LITHOGRAPHIC LATERAL DIMENSION AND METHOD OF FORMING SAME

Patent #:	9761539	Issue Dt:	09/12/2017	Application #:	14753768	Filing Dt:	06/29/2015
Publication #:	US20160379934	Pub Dt:	12/29/2016
Title:	WAFER RIGIDITY WITH REINFORCEMENT STRUCTURE

Patent #:	9245791	Issue Dt:	01/26/2016	Application #:	14754190	Filing Dt:	06/29/2015
Publication #:	US20150318208	Pub Dt:	11/05/2015
Title:	METHOD FOR FABRICATING A CONTACT

Patent #:	10396000	Issue Dt:	08/27/2019	Application #:	14789476	Filing Dt:	07/01/2015
Publication #:	US20170005014	Pub Dt:	01/05/2017
Title:	TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS

Patent #:	9324722	Issue Dt:	04/26/2016	Application #:	14797757	Filing Dt:	07/13/2015
Title:	UTILIZATION OF BLOCK-MASK AND CUT-MASK FOR FORMING METAL ROUTING IN AN IC DEVICE

Patent #:	9647063	Issue Dt:	05/09/2017	Application #:	14797945	Filing Dt:	07/13/2015
Publication #:	US20150318352	Pub Dt:	11/05/2015
Title:	NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS

Patent #:	9337338	Issue Dt:	05/10/2016	Application #:	14820938	Filing Dt:	08/07/2015
Publication #:	US20150349089	Pub Dt:	12/03/2015
Title:	TUCKED ACTIVE REGION WITHOUT DUMMY POLY FOR PERFORMANCE BOOST AND VARIATION REDUCTION

Patent #:	9653356	Issue Dt:	05/16/2017	Application #:	14822340	Filing Dt:	08/10/2015
Publication #:	US20170047253	Pub Dt:	02/16/2017
Title:	METHODS OF FORMING SELF-ALIGNED DEVICE LEVEL CONTACT STRUCTURES

Patent #:	9627272	Issue Dt:	04/18/2017	Application #:	14833813	Filing Dt:	08/24/2015
Publication #:	US20170062281	Pub Dt:	03/02/2017
Title:	PATTERNING SCHEME TO MINIMIZE DRY/WETS STRIP INDUCED DEVICE DEGRADATION

Patent #:	10302414	Issue Dt:	05/28/2019	Application #:	14852897	Filing Dt:	09/14/2015
Publication #:	US20160076876	Pub Dt:	03/17/2016
Title:	SCATTEROMETRY METHOD AND SYSTEM

Patent #:	10262905	Issue Dt:	04/16/2019	Application #:	14867797	Filing Dt:	09/28/2015
Publication #:	US20160020154	Pub Dt:	01/21/2016
Title:	SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS

Patent #:	9633942	Issue Dt:	04/25/2017	Application #:	14939365	Filing Dt:	11/12/2015
Publication #:	US20170141027	Pub Dt:	05/18/2017
Title:	CONDUCTIVELY DOPED POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER

Patent #:	9620380	Issue Dt:	04/11/2017	Application #:	14972804	Filing Dt:	12/17/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SELF-ALIGNED QUADRUPLE PATTERNING

Patent #:	9793168	Issue Dt:	10/17/2017	Application #:	14977387	Filing Dt:	12/21/2015
Publication #:	US20160111335	Pub Dt:	04/21/2016
Title:	SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS

Patent #:	9748352	Issue Dt:	08/29/2017	Application #:	14984688	Filing Dt:	12/30/2015
Publication #:	US20160111513	Pub Dt:	04/21/2016
Title:	MULTI-CHANNEL GATE-ALL-AROUND FET

Patent #:	9910124	Issue Dt:	03/06/2018	Application #:	15015176	Filing Dt:	02/04/2016
Publication #:	US20170227622	Pub Dt:	08/10/2017
Title:	APPARATUS AND METHOD FOR VECTOR S-PARAMETER MEASUREMENTS

Patent #:	10322493	Issue Dt:	06/18/2019	Application #:	15046496	Filing Dt:	02/18/2016
Publication #:	US20160158912	Pub Dt:	06/09/2016
Title:	CHEMICAL MECHANICAL POLISHING APPARATUS

Patent #:	9698262	Issue Dt:	07/04/2017	Application #:	15072130	Filing Dt:	03/16/2016
Publication #:	US20160276478	Pub Dt:	09/22/2016
Title:	VERTICAL FIN FIELD-EFFECT SEMICONDUCTOR DEVICE

Patent #:	9634142	Issue Dt:	04/25/2017	Application #:	15076699	Filing Dt:	03/22/2016
Title:	Method for Improving Boron Diffusion in a Germanium-rich Fin through Germanium Concentration Reduction in Fin S/D Regions by Thermal Mixing

Patent #:	9691626	Issue Dt:	06/27/2017	Application #:	15077384	Filing Dt:	03/22/2016
Title:	METHOD OF FORMING A PATTERN FOR INTERCONNECTION LINES IN AN INTEGRATED CIRCUIT WHEREIN THE PATTERN INCLUDES GAMMA AND BETA BLOCK MASK PORTIONS

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Title:	METHODS OF FORMING MIS CONTACT STRUCTURES ON TRANSISTOR DEVICES IN CMOS APPLICATIONS

Patent #:	10311186	Issue Dt:	06/04/2019	Application #:	15096551	Filing Dt:	04/12/2016
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Title:	THREE-DIMENSIONAL PATTERN RISK SCORING

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Title:	TWO-DIMENSIONAL SELF-ALIGNED SUPER VIA INTEGRATION ON SELF-ALIGNED GATE CONTACT

Patent #:	10276390	Issue Dt:	04/30/2019	Application #:	15097861	Filing Dt:	04/13/2016
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Title:	METHOD AND APPARATUS FOR REDUCING THRESHOLD VOLTAGE MISMATCH IN AN INTEGRATED CIRCUIT

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100

Patent #:	9685529	Issue Dt:	06/20/2017	Application #:	15189476	Filing Dt:	06/22/2016
Title:	III-V NFETs INCLUDING CHANNEL BARRIER LAYERS TO REDUCE BAND-TO-BAND LEAKAGE CURRENT

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

04/10/2020

Assignee

GLOBALFOUNDRIES INC.

P.O. BOX 309, UGLAND HOUSE

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BIRCH, STEWART, KOLASCH & BIRCH, LLP
	8110 GATEHOUSE ROAD, SUITE 100 EAST
	FALLS CHURCH, VA 22042-1248

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