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Reel/Frame:	054479/0842			Pages:	121
		Recorded:	11/19/2020
Attorney Dkt #:	0941-4477M
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 727
Page 8 of 8
Pages: 1 2 3 4 5 6 7 8

Patent #:	10289109	Issue Dt:	05/14/2019	Application #:	15258217	Filing Dt:	09/07/2016
Publication #:	US20170097638	Pub Dt:	04/06/2017
Title:	METHODS OF ERROR DETECTION IN FABRICATION PROCESSES

Patent #:	10256126	Issue Dt:	04/09/2019	Application #:	15272924	Filing Dt:	09/22/2016
Publication #:	US20180082871	Pub Dt:	03/22/2018
Title:	GAS FLOW PROCESS CONTROL SYSTEM AND METHOD USING CRYSTAL MICROBALANCE(S)

Patent #:	9646962	Issue Dt:	05/09/2017	Application #:	15285985	Filing Dt:	10/05/2016
Title:	LOW LEAKAGE GATE CONTROLLED VERTICAL ELECTROSTATIC DISCHARGE PROTECTION DEVICE INTEGRATION WITH A PLANAR FINFET

Patent #:	10331844	Issue Dt:	06/25/2019	Application #:	15290569	Filing Dt:	10/11/2016
Publication #:	US20180102289	Pub Dt:	04/12/2018
Title:	TUNABLE CURRENT RATIO IN A CURRENT MIRROR

Patent #:	10283423	Issue Dt:	05/07/2019	Application #:	15292184	Filing Dt:	10/13/2016
Publication #:	US20170033023	Pub Dt:	02/02/2017
Title:	TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS

Patent #:	10192748	Issue Dt:	01/29/2019	Application #:	15297848	Filing Dt:	10/19/2016
Publication #:	US20180108535	Pub Dt:	04/19/2018
Title:	CONTROLLING OF ETCH DEPTH IN DEEP VIA ETCHING PROCESSES AND RESULTANT STRUCTURES

Patent #:	10134903	Issue Dt:	11/20/2018	Application #:	15343021	Filing Dt:	11/03/2016
Publication #:	US20170077306	Pub Dt:	03/16/2017
Title:	VERTICAL SLIT TRANSISTOR WITH OPTIMIZED AC PERFORMANCE

Patent #:	9748251	Issue Dt:	08/29/2017	Application #:	15352102	Filing Dt:	11/15/2016
Title:	METHODS OF FORMING SEMICONDUCTOR DEVICES USING SEMI-BIDIRECTIONAL PATTERNING

Patent #:	10191112	Issue Dt:	01/29/2019	Application #:	15355256	Filing Dt:	11/18/2016
Publication #:	US20180143248	Pub Dt:	05/24/2018
Title:	EARLY DEVELOPMENT OF A DATABASE OF FAIL SIGNATURES FOR SYSTEMATIC DEFECTS IN INTEGRATED CIRCUIT (IC) CHIPS

Patent #:	10347740	Issue Dt:	07/09/2019	Application #:	15367366	Filing Dt:	12/02/2016
Publication #:	US20170084718	Pub Dt:	03/23/2017
Title:	FIN STRUCTURES AND MULTI-VT SCHEME BASED ON TAPERED FIN AND METHOD TO FORM

Patent #:	10243047	Issue Dt:	03/26/2019	Application #:	15372929	Filing Dt:	12/08/2016
Publication #:	US20180166536	Pub Dt:	06/14/2018
Title:	ACTIVE AND PASSIVE COMPONENTS WITH DEEP TRENCH ISOLATION STRUCTURES

Patent #:	10241502	Issue Dt:	03/26/2019	Application #:	15374453	Filing Dt:	12/09/2016
Publication #:	US20170097635	Pub Dt:	04/06/2017
Title:	METHODS OF ERROR DETECTION IN FABRICATION PROCESSES

Patent #:	10168612	Issue Dt:	01/01/2019	Application #:	15375623	Filing Dt:	12/12/2016
Publication #:	US20180164674	Pub Dt:	06/14/2018
Title:	PHOTOMASK BLANK INCLUDING A THIN CHROMIUM HARDMASK

Patent #:	9892971	Issue Dt:	02/13/2018	Application #:	15392042	Filing Dt:	12/28/2016
Title:	CRACK PREVENT AND STOP FOR THIN GLASS SUBSTRATES

Patent #:	10386714	Issue Dt:	08/20/2019	Application #:	15401299	Filing Dt:	01/09/2017
Publication #:	US20180196340	Pub Dt:	07/12/2018
Title:	CREATING KNOWLEDGE BASE FOR OPTICAL PROXIMITY CORRECTION TO REDUCE SUB-RESOLUTION ASSIST FEATURE PRINTING

Patent #:	9947532	Issue Dt:	04/17/2018	Application #:	15425338	Filing Dt:	02/06/2017
Publication #:	US20170148661	Pub Dt:	05/25/2017
Title:	FORMING ZIG-ZAG TRENCH STRUCTURE TO PREVENT ASPECT RATIO TRAPPING DEFECT ESCAPE

Patent #:	9887133	Issue Dt:	02/06/2018	Application #:	15623758	Filing Dt:	06/15/2017
Publication #:	US20170294349	Pub Dt:	10/12/2017
Title:	TWO-DIMENSIONAL SELF-ALIGNED SUPER VIA INTEGRATION ON SELF-ALIGNED GATE CONTACT

Patent #:	10170553	Issue Dt:	01/01/2019	Application #:	15626241	Filing Dt:	06/19/2017
Publication #:	US20170288033	Pub Dt:	10/05/2017
Title:	SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR

Patent #:	10245667	Issue Dt:	04/02/2019	Application #:	15654130	Filing Dt:	07/19/2017
Publication #:	US20170312841	Pub Dt:	11/02/2017
Title:	CHIP JOINING BY INDUCTION HEATING

Patent #:	10325862	Issue Dt:	06/18/2019	Application #:	15657666	Filing Dt:	07/24/2017
Publication #:	US20180019214	Pub Dt:	01/18/2018
Title:	WAFER RIGIDITY WITH REINFORCEMENT STRUCTURE

Patent #:	10345694	Issue Dt:	07/09/2019	Application #:	15658721	Filing Dt:	07/25/2017
Publication #:	US20170322486	Pub Dt:	11/09/2017
Title:	MODEL-BASED GENERATION OF DUMMY FEATURES

Patent #:	10229918	Issue Dt:	03/12/2019	Application #:	15662594	Filing Dt:	07/28/2017
Publication #:	US20180138187	Pub Dt:	05/17/2018
Title:	METHODS OF FORMING SEMICONDUCTOR DEVICES USING SEMI-BIDIRECTIONAL PATTERNING

Patent #:	9953872	Issue Dt:	04/24/2018	Application #:	15699138	Filing Dt:	09/08/2017
Publication #:	US20180012805	Pub Dt:	01/11/2018
Title:	SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS

Patent #:	10460067	Issue Dt:	10/29/2019	Application #:	15791210	Filing Dt:	10/23/2017
Publication #:	US20190303525	Pub Dt:	10/03/2019
Title:	METHOD OF PATTERNING TARGET LAYER

Patent #:	10283407	Issue Dt:	05/07/2019	Application #:	15817554	Filing Dt:	11/20/2017
Publication #:	US20180090374	Pub Dt:	03/29/2018
Title:	TWO-DIMENSIONAL SELF-ALIGNED SUPER VIA INTEGRATION ON SELF-ALIGNED GATE CONTACT

Patent #:	10325808	Issue Dt:	06/18/2019	Application #:	15858691	Filing Dt:	12/29/2017
Publication #:	US20180182671	Pub Dt:	06/28/2018
Title:	CRACK PREVENT AND STOP FOR THIN GLASS SUBSTRATES

Patent #:	10379191	Issue Dt:	08/13/2019	Application #:	15868248	Filing Dt:	01/11/2018
Publication #:	US20180136304	Pub Dt:	05/17/2018
Title:	APPARATUS AND METHOD FOR VECTOR S-PARAMETER MEASUREMENTS

Assignor

Exec Dt:

04/10/2020

Assignee

P.O. BOX 309, UGLAND HOUSE

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BIRCH, STEWART, KOLASCH & BIRCH, LLP
	8110 GATEHOUSE ROAD, SUITE 100 EAST
	FALLS CHURCH, VA 22042-1248

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