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Patent Assignment Details
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Reel/Frame:012458/0851   Pages: 4
Recorded: 01/09/2002
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
02/28/2006
Application #:
09807500
Filing Dt:
06/11/2001
Title:
AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT
Assignors
1
Exec Dt:
05/11/2001
2
Exec Dt:
05/11/2001
Assignees
1
28 ANG MO KIO INDUSTRIAL PARK 2
569508, SINGAPORE, SINGAPORE
2
SECTOR 16A, INSTITUTIONAL AREA
NOIDA 201 301 UTTAR PRADESH, INDIA
Correspondence name and address
SEED INTELLECTUAL PROPERTY LAW GROUP
MICHAEL J. DONOHUE
701 FIFTH AVENUE, SUITE 6300
SEATTLE, WA 98104-7092

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