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Reel/Frame:035222/0866   Pages: 83
Recorded: 03/18/2015
Attorney Dkt #:40767-149
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 100
Page 1 of 2
Pages: 1 2
1
Patent #:
Issue Dt:
01/10/2006
Application #:
10409543
Filing Dt:
04/08/2003
Title:
FIFO MEMORY WITH PROGRAMMABLE DATA PORT WIDTHS
2
Patent #:
Issue Dt:
04/12/2005
Application #:
10417290
Filing Dt:
04/16/2003
Title:
PROGRAMMABLE LOGIC DEVICE ARCHITECTURE BASED ON ARRAYS OF LUT-BASED BOOLEAN TERMS
3
Patent #:
Issue Dt:
05/17/2005
Application #:
10425862
Filing Dt:
04/28/2003
Title:
PROGRAMMABLE AND FIXED LOGIC CIRCUITRY FOR HIGH-SPEED INTERFACES
4
Patent #:
Issue Dt:
06/07/2005
Application #:
10425863
Filing Dt:
04/28/2003
Title:
SCALABLE DEVICE ARCHITECTURE FOR HIGH-SPEED INTERFACES
5
Patent #:
Issue Dt:
03/01/2005
Application #:
10428885
Filing Dt:
05/01/2003
Title:
CASCADED LOGIC BLOCK ARCHITECTURE FOR COMPLEX PROGRAMMABLE LOGIC DEVICES
6
Patent #:
Issue Dt:
03/08/2005
Application #:
10428888
Filing Dt:
05/01/2003
Title:
MULTI-STAGE INTERCONNECT ARCHITECTURE FOR COMPLEX PROGRAMMABLE LOGIC DEVICES
7
Patent #:
Issue Dt:
04/12/2005
Application #:
10428889
Filing Dt:
05/01/2003
Title:
CPLD WITH MULTI-FUNCTION BLOCKS AND DISTRIBUTED MEMORY
8
Patent #:
Issue Dt:
07/26/2005
Application #:
10428982
Filing Dt:
05/01/2003
Title:
PROGRAMMABLE LOGIC DEVICE WITH ENHANCED WIDE AND DEEP LOGIC CAPABILITY
9
Patent #:
Issue Dt:
12/07/2004
Application #:
10439602
Filing Dt:
05/16/2003
Title:
NON-VOLATILE AND RECONFIGURABLE PROGRAMMABLE LOGIC DEVICES
10
Patent #:
Issue Dt:
05/02/2006
Application #:
10441814
Filing Dt:
05/19/2003
Title:
MEASURING PROPAGATION DELAYS OF PROGRAMMABLE LOGIC DEVICES
11
Patent #:
Issue Dt:
11/27/2007
Application #:
10447120
Filing Dt:
05/28/2003
Title:
SKEW CANCELLATION FOR SOURCE SYNCHRONOUS CLOCK AND DATA SIGNALS
12
Patent #:
Issue Dt:
03/07/2006
Application #:
10447451
Filing Dt:
05/28/2003
Publication #:
Pub Dt:
12/02/2004
Title:
DIGITALLY CONTROLLED DELAY CELLS
13
Patent #:
Issue Dt:
12/04/2007
Application #:
10457630
Filing Dt:
06/09/2003
Title:
INTEGRATED CIRCUIT INCLUDING EXTERNAL ELECTRONIC COMPONENTS WITH LOW INSERTION LOSS
14
Patent #:
Issue Dt:
04/12/2005
Application #:
10459091
Filing Dt:
06/11/2003
Publication #:
Pub Dt:
12/16/2004
Title:
FLEXIBLE MEDIA ACCESS CONTROL ARCHITECTURE
15
Patent #:
Issue Dt:
02/15/2005
Application #:
10460385
Filing Dt:
06/11/2003
Title:
SYNCHRONIZATION OF PROGRAMMABLE MULTIPLEXERS AND DEMULTIPLEXERS
16
Patent #:
Issue Dt:
03/01/2005
Application #:
10463781
Filing Dt:
06/16/2003
Title:
HIGH SPEED INTERFACE FOR A PROGRAMMABLE INTERCONNECT CIRCUIT
17
Patent #:
Issue Dt:
04/19/2005
Application #:
10464083
Filing Dt:
06/18/2003
Publication #:
Pub Dt:
12/23/2004
Title:
BI-DIRECTIONAL BUFFERING FOR MEMORY DATA LINES
18
Patent #:
Issue Dt:
11/23/2004
Application #:
10600042
Filing Dt:
06/20/2003
Title:
INTEGRATED CIRCUIT AND ASSOCIATED DESIGN METHOD USING SPARE GATE ISLANDS
19
Patent #:
Issue Dt:
12/20/2005
Application #:
10610253
Filing Dt:
06/30/2003
Title:
HIGH-PERFORMANCE NON-VOLATILE MEMORY DEVICE AND FABRICATION PROCESS
20
Patent #:
Issue Dt:
11/07/2006
Application #:
10613460
Filing Dt:
07/03/2003
Title:
NOISE-SHIELDING, SWITCH-CONTROLLED LOAD CIRCUITRY FOR OSCILLATORS AND THE LIKE
21
Patent #:
Issue Dt:
10/04/2005
Application #:
10613462
Filing Dt:
07/03/2003
Title:
PROGRAMMABLE I/O INTERFACES FOR FPGAS AND OTHER PLDS
22
Patent #:
Issue Dt:
10/25/2005
Application #:
10617980
Filing Dt:
07/10/2003
Title:
PROGRAMMABLE LOGIC DEVICE WITH HARDWIRED MICROSEQUENCER
23
Patent #:
Issue Dt:
08/29/2006
Application #:
10619645
Filing Dt:
07/14/2003
Title:
SCALABLE SERIALIZER-DESERIALIZER ARCHITECTURE AND PROGRAMMABLE INTERFACE
24
Patent #:
Issue Dt:
06/07/2005
Application #:
10619711
Filing Dt:
07/14/2003
Title:
PROGRAMMABLE LOGIC DEVICE WITH ENHANCED WIDE INPUT PRODUCT TERM CASCADING
25
Patent #:
Issue Dt:
04/18/2006
Application #:
10620147
Filing Dt:
07/14/2003
Title:
ALGORITHM TO INCREASE LOGIC INPUT WIDTH BY CASCADING PRODUCT TERMS
26
Patent #:
Issue Dt:
07/19/2005
Application #:
10620286
Filing Dt:
07/14/2003
Title:
FIELD PROGRAMMABLE GATE ARRAY HAVING EMBEDDED MEMORY WITH CONFIGURABLE DEPTH AND WIDTH
27
Patent #:
Issue Dt:
09/06/2005
Application #:
10624965
Filing Dt:
07/21/2003
Title:
PROGRAMMABLE LOGIC DEVICE WITH A MEMORY-BASED FINITE STATE MACHINE
28
Patent #:
Issue Dt:
05/18/2004
Application #:
10626089
Filing Dt:
07/24/2003
Title:
ZERO POWER MEMORY CELL WITH REDUCED THRESHOLD VOLTAGE
29
Patent #:
Issue Dt:
11/29/2005
Application #:
10628656
Filing Dt:
07/28/2003
Title:
PROGRAMMABLE LOCK DETECTOR AND CORRECTOR
30
Patent #:
Issue Dt:
08/02/2005
Application #:
10628657
Filing Dt:
07/28/2003
Title:
PROGRAMMABLE SIGNAL TERMINATION FOR FPGAS AND THE LIKE
31
Patent #:
Issue Dt:
04/26/2005
Application #:
10629221
Filing Dt:
07/29/2003
Publication #:
Pub Dt:
02/03/2005
Title:
CLOCK GENERATOR WITH SKEW CONTROL
32
Patent #:
Issue Dt:
03/28/2006
Application #:
10629223
Filing Dt:
07/29/2003
Publication #:
Pub Dt:
02/03/2005
Title:
CLOCK GENERATOR
33
Patent #:
Issue Dt:
06/07/2005
Application #:
10629512
Filing Dt:
07/29/2003
Publication #:
Pub Dt:
02/03/2005
Title:
MEMORY ACCESS VIA SERIAL MEMORY INTERFACE
34
Patent #:
Issue Dt:
04/12/2005
Application #:
10640804
Filing Dt:
08/13/2003
Title:
INTEGRATED CIRCUIT AND ASSOCIATED DESIGN METHOD WITH ANTENNA ERROR CONTROL USING SPARE GATES
35
Patent #:
Issue Dt:
01/04/2005
Application #:
10640828
Filing Dt:
08/13/2003
Title:
ENHANCED CPLD MACROCELL MODULE HAVING SELECTABLE BYPASS OF STEERING-BASED RESOURCE ALLOCATION
36
Patent #:
Issue Dt:
09/06/2005
Application #:
10641260
Filing Dt:
08/13/2003
Publication #:
Pub Dt:
02/17/2005
Title:
PROGRAMMABLE BROADCAST INITIALIZATION OF MEMORY BLOCKS
37
Patent #:
Issue Dt:
08/02/2005
Application #:
10642370
Filing Dt:
08/15/2003
Publication #:
Pub Dt:
02/17/2005
Title:
FIELD PROGRAMMABLE GATE ARRAY
38
Patent #:
Issue Dt:
01/11/2005
Application #:
10655686
Filing Dt:
09/04/2003
Title:
SHARED TRANSMISSION LINE COMMUNICATION SYSTEM AND METHOD
39
Patent #:
Issue Dt:
05/02/2006
Application #:
10660814
Filing Dt:
09/12/2003
Title:
DELAY-MATCHED ASIC CONVERSION OF A PROGRAMMABLE LOGIC DEVICE
40
Patent #:
Issue Dt:
11/29/2005
Application #:
10665920
Filing Dt:
09/18/2003
Title:
CONTROLLED HYSTERESIS COMPARATOR WITH RAIL-TO-RAIL INPUT
41
Patent #:
Issue Dt:
09/13/2005
Application #:
10671363
Filing Dt:
09/25/2003
Title:
PROGRAMMABLE I/O STRUCTURE FOR FPGAS AND THE LIKE HAVING SHARED CIRCUITRY
42
Patent #:
Issue Dt:
09/13/2005
Application #:
10671378
Filing Dt:
09/25/2003
Title:
PROGRAMMABLE I/O STRUCTURE FOR FPGAS AND THE LIKE HAVING REDUCED PAD CAPACITANCE
43
Patent #:
Issue Dt:
06/21/2005
Application #:
10671756
Filing Dt:
09/26/2003
Title:
MULTIPORT MEMORY WITH TWISTED BITLINES
44
Patent #:
Issue Dt:
09/11/2007
Application #:
10676536
Filing Dt:
09/30/2003
Title:
SEMICONDUCTOR DEVICE ADAPTED FOR FORMING MULTIPLE SCAN CHAINS
45
Patent #:
Issue Dt:
10/26/2004
Application #:
10687468
Filing Dt:
10/15/2003
Title:
ANALOG-TO-DIGITAL CONVERTERS
46
Patent #:
Issue Dt:
06/27/2006
Application #:
10699321
Filing Dt:
10/31/2003
Publication #:
Pub Dt:
05/05/2005
Title:
LATERAL HIGH-VOLTAGE JUNCTION DEVICE
47
Patent #:
Issue Dt:
08/15/2006
Application #:
10701005
Filing Dt:
11/03/2003
Title:
CLOCK GENERATION
48
Patent #:
Issue Dt:
08/08/2006
Application #:
10704025
Filing Dt:
11/06/2003
Title:
PROGRAMMABLE LOGIC DEVICE WITH FLEXIBLE MEMORY ALLOCATION AND ROUTING
49
Patent #:
Issue Dt:
08/29/2006
Application #:
10726972
Filing Dt:
12/03/2003
Title:
PROGRAMMABLE POWER MANAGEMENT SYSTEM AND METHOD
50
Patent #:
Issue Dt:
03/06/2007
Application #:
10728685
Filing Dt:
12/05/2003
Title:
POWER SUPPLY REMOTE VOLTAGE SENSING
51
Patent #:
Issue Dt:
01/03/2006
Application #:
10737514
Filing Dt:
12/16/2003
Title:
LINEAR THERMOELECTRIC DEVICE DRIVER
52
Patent #:
Issue Dt:
11/07/2006
Application #:
10744353
Filing Dt:
12/22/2003
Title:
METHOD FOR CONFIGURING MULTIPLE-OUTPUT PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER
53
Patent #:
Issue Dt:
03/28/2006
Application #:
10768643
Filing Dt:
01/30/2004
Publication #:
Pub Dt:
08/04/2005
Title:
OUTPUT STAGES FOR HIGH CURRENT LOW NOISE BANDGAP REFERENCE CIRCUIT IMPLEMENTATIONS
54
Patent #:
Issue Dt:
04/04/2006
Application #:
10769174
Filing Dt:
01/29/2004
Publication #:
Pub Dt:
08/04/2005
Title:
ELECTROSTATIC DISCHARGE SIMULATION
55
Patent #:
Issue Dt:
12/06/2005
Application #:
10782564
Filing Dt:
02/18/2004
Publication #:
Pub Dt:
08/04/2005
Title:
COMBINATION FIELD PROGRAMMABLE GATE ARRAY ALLOWING DYNAMIC REPROGRAMMABILITY AND NON-VOLATILE PROGRAMMABILITY BASED UPON TRANSISTOR GATE OXIDE BREAKDOWN
56
Patent #:
Issue Dt:
07/25/2006
Application #:
10783886
Filing Dt:
02/20/2004
Publication #:
Pub Dt:
09/01/2005
Title:
UPGRADEABLE AND RECONFIGURABLE PROGRAMMABLE LOGIC DEVICE
57
Patent #:
Issue Dt:
03/13/2007
Application #:
10791073
Filing Dt:
03/01/2004
Title:
FAST DIAGONAL INTERLEAVED PARITY (DIP) CALCULATOR
58
Patent #:
Issue Dt:
08/14/2007
Application #:
10794079
Filing Dt:
03/04/2004
Publication #:
Pub Dt:
09/08/2005
Title:
TIMER SYSTEMS AND METHODS
59
Patent #:
Issue Dt:
04/11/2006
Application #:
10794498
Filing Dt:
03/05/2004
Publication #:
Pub Dt:
09/08/2005
Title:
POWERING-UP A DEVICE HAVING DIGITAL AND ANALOG CIRCUITRY
60
Patent #:
Issue Dt:
03/21/2006
Application #:
10794524
Filing Dt:
03/05/2004
Publication #:
Pub Dt:
09/08/2005
Title:
SYSTEMS AND METHODS FOR CONTROLLING VOLTAGE REGULATOR MODULE POWER SUPPLIES
61
Patent #:
Issue Dt:
06/27/2006
Application #:
10797759
Filing Dt:
03/09/2004
Publication #:
Pub Dt:
09/15/2005
Title:
SENSE AMPLIFIER SYSTEMS AND METHODS
62
Patent #:
Issue Dt:
06/19/2007
Application #:
10809180
Filing Dt:
03/25/2004
Title:
TABLE-BASED SCHEDULER FOR FIFOS AND THE LIKE
63
Patent #:
Issue Dt:
08/22/2006
Application #:
10809658
Filing Dt:
03/25/2004
Title:
CONFIGURING FPGAS AND THE LIKE USING ONE OR MORE SERIAL MEMORY DEVICES
64
Patent #:
Issue Dt:
01/23/2007
Application #:
10815403
Filing Dt:
03/31/2004
Title:
SELF-ADJUSTING SCHMITT TRIGGER
65
Patent #:
Issue Dt:
07/25/2006
Application #:
10817215
Filing Dt:
04/02/2004
Publication #:
Pub Dt:
10/06/2005
Title:
CHARGE PUMP FOR A LOW-VOLTAGE WIDE-TUNING RANGE PHASE-LOCKED LOOP
66
Patent #:
Issue Dt:
02/14/2006
Application #:
10829865
Filing Dt:
04/21/2004
Title:
DYNAMIC GAIN ADJUSTMENT SYSTEMS AND METHODS FOR METASTABILITY RESISTANCE
67
Patent #:
Issue Dt:
02/14/2006
Application #:
10834528
Filing Dt:
04/29/2004
Title:
LOW PASS FILTER SYSTEMS AND METHODS
68
Patent #:
Issue Dt:
12/11/2007
Application #:
10837086
Filing Dt:
04/30/2004
Title:
HIGH-VOLTAGE PROTECTION DEVICE AND PROCESS
69
Patent #:
Issue Dt:
05/29/2007
Application #:
10841987
Filing Dt:
05/07/2004
Publication #:
Pub Dt:
11/10/2005
Title:
SWITCHED CAPACITOR RIPPLE-SMOOTHING FILTER
70
Patent #:
Issue Dt:
02/21/2006
Application #:
10842345
Filing Dt:
05/07/2004
Publication #:
Pub Dt:
11/10/2005
Title:
CONTROL SIGNAL GENERATION FOR A LOW JITTER SWITCHED-CAPACITOR FREQUENCY SYNTHESIZER
71
Patent #:
Issue Dt:
06/13/2006
Application #:
10843708
Filing Dt:
05/12/2004
Title:
I/O BUFFER ARCHITECTURE FOR PROGRAMMABLE DEVICES
72
Patent #:
Issue Dt:
03/27/2007
Application #:
10856100
Filing Dt:
05/28/2004
Publication #:
Pub Dt:
12/01/2005
Title:
CURRENT MODE LOGIC BUFFER
73
Patent #:
Issue Dt:
06/20/2006
Application #:
10857667
Filing Dt:
05/28/2004
Publication #:
Pub Dt:
08/04/2005
Title:
COMBINATION FIELD PROGRAMMABLE GATE ARRAY ALLOWING DYNAMIC REPROGRAMMABILITY
74
Patent #:
Issue Dt:
10/03/2006
Application #:
10885419
Filing Dt:
07/06/2004
Publication #:
Pub Dt:
01/12/2006
Title:
MEMORY SYSTEMS AND METHODS
75
Patent #:
Issue Dt:
05/08/2007
Application #:
10910091
Filing Dt:
08/03/2004
Publication #:
Pub Dt:
02/09/2006
Title:
BYTE ENABLE LOGIC FOR MEMORY
76
Patent #:
Issue Dt:
12/30/2008
Application #:
10912943
Filing Dt:
08/06/2004
Publication #:
Pub Dt:
02/09/2006
Title:
DATA TRANSMISSION SYNCHRONIZATION
77
Patent #:
Issue Dt:
07/18/2006
Application #:
10928563
Filing Dt:
08/27/2004
Title:
PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING ELECTRICALLY ISOLATED LOW VOLTAGE AND HIGH VOLTAGE REGIONS
78
Patent #:
Issue Dt:
01/27/2009
Application #:
10929199
Filing Dt:
08/30/2004
Publication #:
Pub Dt:
03/16/2006
Title:
TESTING EMBEDDED MEMORY IN AN INTEGRATED CIRCUIT
79
Patent #:
Issue Dt:
11/14/2006
Application #:
10944978
Filing Dt:
09/20/2004
Publication #:
Pub Dt:
03/23/2006
Title:
FIELD PROGRAMMABLE GATE ARRAYS USING BOTH VOLATILE AND NONVOLATILE MEMORY CELL PROPERTIES AND THEIR CONTROL
80
Patent #:
Issue Dt:
12/12/2006
Application #:
10973750
Filing Dt:
10/25/2004
Publication #:
Pub Dt:
04/27/2006
Title:
MEMORY OUTPUT DATA SYSTEMS AND METHODS WITH FEEDBACK
81
Patent #:
Issue Dt:
01/16/2007
Application #:
10974107
Filing Dt:
10/26/2004
Publication #:
Pub Dt:
12/15/2005
Title:
FIELD PROGRAMMABLE GATE ARRAY LOGIC UNIT AND ITS CLUSTER
82
Patent #:
Issue Dt:
10/31/2006
Application #:
10974305
Filing Dt:
10/27/2004
Title:
PROGRAMMABLE LOGIC DEVICE HAVING A CONFIGURABLE DRAM WITH TRANSPARENT REFRESH
83
Patent #:
Issue Dt:
12/11/2007
Application #:
10974453
Filing Dt:
10/25/2004
Title:
VARIABLE DATA WIDTH MEMORY SYSTEMS AND METHODS
84
Patent #:
Issue Dt:
05/20/2008
Application #:
10978899
Filing Dt:
11/01/2004
Title:
TESTING EMBEDDED MEMORY IN INTEGRATED CIRCUITS SUCH AS PROGRAMMABLE LOGIC CIRCUIT
85
Patent #:
Issue Dt:
01/09/2007
Application #:
10996283
Filing Dt:
11/22/2004
Title:
LOW POWER ASYNCHRONOUS SENSE AMP
86
Patent #:
Issue Dt:
06/12/2007
Application #:
11007954
Filing Dt:
12/09/2004
Title:
DYNAMIC OVER-VOLTAGE PROTECTION SCHEME FOR INTEGRATED-CIRCUIT DEVICES
87
Patent #:
Issue Dt:
05/08/2007
Application #:
11012548
Filing Dt:
12/15/2004
Title:
PROGRAMMABLE CURRENT OUTPUT BUFFER
88
Patent #:
Issue Dt:
05/08/2007
Application #:
11012550
Filing Dt:
12/15/2004
Title:
INTERFACE CIRCUITRY FOR ELECTRICAL SYSTEMS
89
Patent #:
Issue Dt:
02/13/2007
Application #:
11015265
Filing Dt:
12/16/2004
Title:
INITIALIZING MEMORY BLOCKS
90
Patent #:
Issue Dt:
02/13/2007
Application #:
11015369
Filing Dt:
12/17/2004
Title:
SENSE AMPLIFIER TIMING
91
Patent #:
Issue Dt:
03/06/2007
Application #:
11016665
Filing Dt:
12/17/2004
Title:
CASCADABLE MEMORY
92
Patent #:
Issue Dt:
08/14/2007
Application #:
11036630
Filing Dt:
01/13/2005
Title:
SELF-VERIFICATION OF CONFIGURATION MEMORY IN PROGRAMMABLE LOGIC DEVICES
93
Patent #:
Issue Dt:
07/10/2007
Application #:
11036738
Filing Dt:
01/14/2005
Title:
EEPROM DEVICE WITH VOLTAGE-LIMITING CHARGE PUMP CIRCUIT
94
Patent #:
Issue Dt:
04/24/2007
Application #:
11040772
Filing Dt:
01/20/2005
Title:
SERDES WITH PROGRAMMABLE I/O ARCHITECTURE
95
Patent #:
Issue Dt:
02/27/2007
Application #:
11041319
Filing Dt:
01/24/2005
Title:
SYNCHRONOUS MEMORY
96
Patent #:
Issue Dt:
09/19/2006
Application #:
11044089
Filing Dt:
01/27/2005
Title:
SYNCHRONIZATION OF PROGRAMMABLE MULTIPLEXERS AND DEMULTIPLEXERS
97
Patent #:
Issue Dt:
09/19/2006
Application #:
11044149
Filing Dt:
01/27/2005
Title:
SYNCHRONIZATION OF PROGRAMMABLE MULTIPLEXERS AND DEMULTIPLEXERS
98
Patent #:
Issue Dt:
04/25/2006
Application #:
11044508
Filing Dt:
01/27/2005
Title:
CLOCK GENERATOR WITH SKEW CONTROL
99
Patent #:
Issue Dt:
05/22/2007
Application #:
11054011
Filing Dt:
02/09/2005
Title:
MULTI-PORT MEMORY SYSTEMS AND METHODS FOR BIT LINE COUPLING
100
Patent #:
Issue Dt:
12/13/2005
Application #:
11055280
Filing Dt:
02/10/2005
Title:
PROGRAMMABLE LOGIC DEVICES WITH INTEGRATED STANDARD-CELL LOGIC BLOCKS
Assignors
1
Exec Dt:
03/10/2015
2
Exec Dt:
03/10/2015
3
Exec Dt:
03/10/2015
4
Exec Dt:
03/10/2015
Assignee
1
520 MADISON AVENUE
NEW YORK, NEW YORK 10022
Correspondence name and address
PROSKAUER ROSE LLP
ONE INTERNATIONAL PLACE
BOSTON, MA 02110

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