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Patent #:
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Issue Dt:
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09/27/2016
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Application #:
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14943118
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Filing Dt:
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11/17/2015
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Title:
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CONTROLLED SPALLING OF FINE FEATURES
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Patent #:
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Issue Dt:
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07/18/2017
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Application #:
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14963446
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Filing Dt:
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12/09/2015
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Publication #:
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Pub Dt:
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06/15/2017
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Title:
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DUAL ISOLATION FIN AND METHOD OF MAKING
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Patent #:
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Issue Dt:
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02/14/2017
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Application #:
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14974123
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Filing Dt:
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12/18/2015
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Title:
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CAPACITOR IN STRAIN RELAXED BUFFER
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Patent #:
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Issue Dt:
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08/15/2017
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Application #:
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14974537
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Filing Dt:
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12/18/2015
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Publication #:
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Pub Dt:
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06/22/2017
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Title:
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CHANNEL REPLACEMENT AND BIMODAL DOPING SCHEME FOR BULK FINFET THRESHOLD VOLTAGE MODULATION WITH REDUCED PERFORMANCE PENALTY
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Patent #:
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Issue Dt:
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09/05/2017
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Application #:
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14977945
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Filing Dt:
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12/22/2015
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Publication #:
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Pub Dt:
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06/22/2017
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Title:
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INTERLEVEL AIRGAP DIELECTRIC
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Patent #:
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Issue Dt:
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04/04/2017
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Application #:
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14978362
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Filing Dt:
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12/22/2015
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Title:
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NANOWIRE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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05/30/2017
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Application #:
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14978430
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Filing Dt:
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12/22/2015
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Publication #:
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Pub Dt:
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06/22/2017
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Title:
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SUPERLATTICE LATERAL BIPOLAR JUNCTION TRANSISTOR
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Patent #:
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Issue Dt:
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01/03/2017
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Application #:
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14983643
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Filing Dt:
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12/30/2015
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Title:
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JUNCTIONLESS BACK END OF THE LINE VIA CONTACT
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Patent #:
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Issue Dt:
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10/31/2017
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Application #:
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14985943
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Filing Dt:
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12/31/2015
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Publication #:
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Pub Dt:
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07/06/2017
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Title:
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BOTTOM SOURCE/DRAIN SILICIDATION FOR VERTICAL FIELD-EFFECT TRANSISTOR (FET)
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Patent #:
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Issue Dt:
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06/12/2018
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Application #:
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15015389
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Filing Dt:
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02/04/2016
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Publication #:
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Pub Dt:
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08/10/2017
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Title:
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COLUMNAR INTERCONNECTS AND METHOD OF MAKING THEM
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Patent #:
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Issue Dt:
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11/15/2016
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Application #:
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15018387
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Filing Dt:
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02/08/2016
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Title:
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RECESSED METAL LINER CONTACT WITH COPPER FILL
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Patent #:
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Issue Dt:
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04/17/2018
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Application #:
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15042908
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Filing Dt:
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02/12/2016
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Publication #:
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Pub Dt:
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08/17/2017
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Title:
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TUNNELING FIN TYPE FIELD EFFECT TRANSISTOR WITH EPITAXIAL SOURCE AND DRAIN REGIONS
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Patent #:
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Issue Dt:
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10/17/2017
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Application #:
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15044258
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Filing Dt:
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02/16/2016
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Publication #:
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Pub Dt:
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08/17/2017
| | | | |
Title:
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ION FLOW BARRIER STRUCTURE FOR INTERCONNECT METALLIZATION
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Patent #:
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Issue Dt:
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04/09/2019
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Application #:
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15045778
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Filing Dt:
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02/17/2016
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Publication #:
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Pub Dt:
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08/17/2017
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Title:
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DUAL WORK FUNCTION CMOS DEVICES
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Patent #:
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Issue Dt:
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05/30/2017
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Application #:
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15050975
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Filing Dt:
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02/23/2016
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Title:
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BEOL VERTICAL FUSE FORMED OVER AIR GAP
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Patent #:
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Issue Dt:
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08/28/2018
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Application #:
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15051790
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Filing Dt:
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02/24/2016
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Publication #:
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Pub Dt:
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08/24/2017
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Title:
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PATTERNED GATE DIELECTRICS FOR III-V-BASED CMOS CIRCUITS
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Patent #:
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Issue Dt:
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02/21/2017
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Application #:
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15053106
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Filing Dt:
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02/25/2016
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Title:
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CONTACT AREA STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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05/08/2018
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Application #:
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15054005
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Filing Dt:
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02/25/2016
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Publication #:
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Pub Dt:
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08/31/2017
| | | | |
Title:
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FORMING NANOTIPS
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Patent #:
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Issue Dt:
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01/30/2018
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Application #:
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15059516
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Filing Dt:
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03/03/2016
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Publication #:
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Pub Dt:
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09/07/2017
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Title:
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WELL AND PUNCH THROUGH STOPPER FORMATION USING CONFORMAL DOPING
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Patent #:
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Issue Dt:
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04/04/2017
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Application #:
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15060124
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Filing Dt:
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03/03/2016
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Title:
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VERTICAL FINFET WITH STRAINED CHANNEL
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Patent #:
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Issue Dt:
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08/15/2017
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Application #:
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15067996
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Filing Dt:
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03/11/2016
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Title:
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ROBUST HIGH PERFORMANCE LOW HYDROGEN SILICON CARBON NITRIDE (SiCNH) DIELECTRICS FOR NANO ELECTRONIC DEVICES
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Patent #:
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Issue Dt:
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06/19/2018
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Application #:
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15079368
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Filing Dt:
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03/24/2016
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Publication #:
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Pub Dt:
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09/28/2017
| | | | |
Title:
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HIGH PERFORMANCE MIDDLE OF LINE INTERCONNECTS
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Patent #:
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Issue Dt:
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06/20/2017
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Application #:
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15082150
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Filing Dt:
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03/28/2016
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Title:
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TOP METAL CONTACT FOR VERTICAL TRANSISTOR STRUCTURES
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Patent #:
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Issue Dt:
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04/02/2019
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Application #:
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15082646
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Filing Dt:
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03/28/2016
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Publication #:
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Pub Dt:
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09/28/2017
| | | | |
Title:
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SINGLE PROCESS FOR LINER AND METAL FILL
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Patent #:
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Issue Dt:
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05/16/2017
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Application #:
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15086908
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Filing Dt:
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03/31/2016
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Title:
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VERTICAL AIR GAP SUBTRACTIVE ETCH BACK END METAL
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Patent #:
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Issue Dt:
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06/06/2017
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Application #:
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15097548
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Filing Dt:
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04/13/2016
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Title:
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LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE
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Patent #:
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Issue Dt:
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06/20/2017
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Application #:
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15134534
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Filing Dt:
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04/21/2016
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Title:
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FORMING CHAMFERLESS VIAS USING THERMALLY DECOMPOSABLE POREFILLER
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Patent #:
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Issue Dt:
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08/01/2017
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Application #:
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15138651
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Filing Dt:
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04/26/2016
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Title:
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VERTICAL FIELD EFFECT TRANSISTORS WITH BOTTOM CONTACT METAL DIRECTLY BENEATH FINS
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Patent #:
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Issue Dt:
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07/17/2018
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Application #:
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15153226
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Filing Dt:
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05/12/2016
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Publication #:
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Pub Dt:
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11/16/2017
| | | | |
Title:
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FIN PATTERNS WITH VARYING SPACING WITHOUT FIN CUT
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Patent #:
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Issue Dt:
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04/09/2019
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Application #:
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15157917
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Filing Dt:
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05/18/2016
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Publication #:
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Pub Dt:
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11/23/2017
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Title:
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DUMMY DIELECTRIC FINS FOR FINFETS WITH SILICON AND SILICON GERMANIUM CHANNELS
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Patent #:
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Issue Dt:
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05/30/2017
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Application #:
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15158196
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Filing Dt:
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05/18/2016
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Title:
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CONTAINED PUNCH THROUGH STOPPER FOR CMOS STRUCTURES ON A STRAIN RELAXED BUFFER SUBSTRATE
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Patent #:
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Issue Dt:
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03/07/2017
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Application #:
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15161868
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Filing Dt:
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05/23/2016
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Title:
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FIN CUT ENABLING SINGLE DIFFUSION BREAKS
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Patent #:
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Issue Dt:
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08/08/2017
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Application #:
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15164420
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Filing Dt:
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05/25/2016
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Title:
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HIGH DENSITY PROGRAMMABLE E-FUSE CO-INTEGRATED WITH VERTICAL FETS
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Patent #:
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Issue Dt:
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06/19/2018
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Application #:
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15174334
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Filing Dt:
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06/06/2016
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Publication #:
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Pub Dt:
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12/07/2017
| | | | |
Title:
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Techniques for Forming FINFET Transistors with Same Fin Pitch and Different Source/Drain Epitaxy Configurations
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Patent #:
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Issue Dt:
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12/05/2017
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Application #:
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15175555
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Filing Dt:
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06/07/2016
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Publication #:
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Pub Dt:
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12/07/2017
| | | | |
Title:
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AVOIDING GATE METAL VIA SHORTING TO SOURCE OR DRAIN CONTACTS
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Patent #:
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Issue Dt:
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09/26/2017
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Application #:
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15176286
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Filing Dt:
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06/08/2016
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Title:
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ALIGNING CONDUCTIVE VIAS WITH TRENCHES
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Patent #:
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Issue Dt:
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01/16/2018
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Application #:
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15176548
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Filing Dt:
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06/08/2016
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Publication #:
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Pub Dt:
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12/14/2017
| | | | |
Title:
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POWER DECOUPLING ATTACHMENT
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Patent #:
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Issue Dt:
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02/19/2019
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Application #:
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15176982
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Filing Dt:
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06/08/2016
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Publication #:
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Pub Dt:
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12/14/2017
| | | | |
Title:
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MULTI TIME PROGRAMMABLE MEMORIES USING LOCAL IMPLANTATION IN HIGH-K/ METAL GATE TECHNOLOGIES
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Patent #:
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Issue Dt:
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09/25/2018
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Application #:
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15177358
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Filing Dt:
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06/09/2016
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Publication #:
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Pub Dt:
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12/14/2017
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Title:
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FABRICATION OF A VERTICAL TRANSISTOR WITH SELF-ALIGNED BOTTOM SOURCE/DRAIN
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Patent #:
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|
Issue Dt:
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01/23/2018
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Application #:
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15178245
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Filing Dt:
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06/09/2016
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Publication #:
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Pub Dt:
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12/14/2017
| | | | |
Title:
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FORMING A STACKED CAPACITOR
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Patent #:
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|
Issue Dt:
|
02/14/2017
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Application #:
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15180171
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Filing Dt:
|
06/13/2016
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Title:
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RECESSED METAL LINER CONTACT WITH COPPER FILL
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Patent #:
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|
Issue Dt:
|
07/24/2018
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Application #:
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15180499
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Filing Dt:
|
06/13/2016
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Publication #:
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|
Pub Dt:
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06/22/2017
| | | | |
Title:
|
CHANNEL REPLACEMENT AND BIMODAL DOPING SCHEME FOR BULK FINFET THRESHOLD VOLTAGE MODULATION WITH REDUCED PERFORMANCE PENALTY
|
|
|
Patent #:
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|
Issue Dt:
|
10/31/2017
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Application #:
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15185807
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Filing Dt:
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06/17/2016
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Title:
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On-Chip DC-DC Power Converters with Fully Integrated GaN Power Switches, Silicon CMOS Transistors and Magnetic Inductors
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Patent #:
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Issue Dt:
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09/19/2017
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Application #:
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15187152
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Filing Dt:
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06/20/2016
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Title:
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METHOD AND STRUCTURE TO ENABLE DUAL CHANNEL FIN CRITICAL DIMENSION CONTROL
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Patent #:
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Issue Dt:
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12/12/2017
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Application #:
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15189749
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Filing Dt:
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06/22/2016
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Publication #:
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Pub Dt:
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12/28/2017
| | | | |
Title:
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REFLOW ENHANCEMENT LAYER FOR METALLIZATION STRUCTURES
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Patent #:
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|
Issue Dt:
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01/02/2018
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Application #:
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15191828
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Filing Dt:
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06/24/2016
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Publication #:
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Pub Dt:
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12/28/2017
| | | | |
Title:
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SIDEWALL IMAGE TRANSFER STRUCTURES
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Patent #:
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|
Issue Dt:
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10/24/2017
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Application #:
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15192196
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Filing Dt:
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06/24/2016
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Title:
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SELECTIVE SPUTTERING WITH LIGHT MASS IONS TO SHARPEN SIDEWALL OF SUBTRACTIVELY PATTERNED CONDUCTIVE METAL LAYER
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Patent #:
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Issue Dt:
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03/13/2018
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Application #:
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15193759
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Filing Dt:
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06/27/2016
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Publication #:
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Pub Dt:
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12/28/2017
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Title:
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SINGLE OR MUTLI BLOCK MASK MANAGEMENT FOR SPACER HEIGHT AND DEFECT REDUCTION FOR BEOL
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Patent #:
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Issue Dt:
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12/18/2018
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Application #:
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15196299
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Filing Dt:
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06/29/2016
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Publication #:
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Pub Dt:
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01/04/2018
| | | | |
Title:
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HIGH ASPECT RATIO GATES
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Patent #:
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Issue Dt:
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05/29/2018
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Application #:
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15196591
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Filing Dt:
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06/29/2016
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Publication #:
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Pub Dt:
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01/04/2018
| | | | |
Title:
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METHOD AND STRUCTURE FOR FORMING MOSFET WITH REDUCED PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
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03/19/2019
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Application #:
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15196774
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Filing Dt:
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06/29/2016
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Publication #:
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Pub Dt:
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01/04/2018
| | | | |
Title:
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VERTICAL TRANSISTOR WITH VARIABLE GATE LENGTH
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Patent #:
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Issue Dt:
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11/27/2018
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Application #:
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15198128
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Filing Dt:
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06/30/2016
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Publication #:
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Pub Dt:
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01/04/2018
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Title:
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VERTICAL CMOS DEVICES WITH COMMON GATE STACKS
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Patent #:
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Issue Dt:
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10/17/2017
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Application #:
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15201490
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Filing Dt:
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07/03/2016
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Title:
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AGGRESSIVE TIP-TO-TIP SCALING USING SUBTRACTIVE INTEGRATON
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Patent #:
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Issue Dt:
|
12/05/2017
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Application #:
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15202475
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Filing Dt:
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07/05/2016
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Title:
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FORMING DEEP AIRGAPS WITHOUT FLOP OVER
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Patent #:
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Issue Dt:
|
08/29/2017
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Application #:
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15202656
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Filing Dt:
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07/06/2016
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Title:
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HYBRID INTERCONNECTS AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
|
09/12/2017
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Application #:
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15218322
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Filing Dt:
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07/25/2016
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Title:
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INTERCONNECT STRUCTURE AND FABRICATION THEREOF
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Patent #:
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Issue Dt:
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07/24/2018
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Application #:
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15218445
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Filing Dt:
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07/25/2016
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Publication #:
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Pub Dt:
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01/25/2018
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Title:
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INTEGRATING METAL-INSULATOR-METAL CAPACITORS WITH AIR GAP PROCESS FLOW
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Patent #:
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Issue Dt:
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03/12/2019
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Application #:
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15223092
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Filing Dt:
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07/29/2016
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Publication #:
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Pub Dt:
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02/01/2018
| | | | |
Title:
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THIN SRAM CELL HAVING VERTICAL TRANSISTORS
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Patent #:
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Issue Dt:
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01/23/2018
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Application #:
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15225003
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Filing Dt:
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08/01/2016
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Publication #:
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Pub Dt:
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02/01/2018
| | | | |
Title:
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METHOD AND STRUCTURE OF FORMING LOW RESISTANCE INTERCONNECTS
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Patent #:
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Issue Dt:
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10/17/2017
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Application #:
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15226834
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Filing Dt:
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08/02/2016
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Title:
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FABRICATION OF A STRAINED REGION ON A SUBSTRATE
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Patent #:
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Issue Dt:
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11/28/2017
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Application #:
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15226971
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Filing Dt:
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08/03/2016
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Title:
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HEAT SINK FOR SEMICONDUCTOR MODULES
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Patent #:
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Issue Dt:
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04/17/2018
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Application #:
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15229783
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Filing Dt:
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08/05/2016
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Publication #:
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Pub Dt:
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02/08/2018
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Title:
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STRUCTURE AND METHOD TO REDUCE COPPER LOSS DURING METAL CAP FORMATION
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Patent #:
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Issue Dt:
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05/15/2018
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Application #:
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15230443
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Filing Dt:
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08/07/2016
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Publication #:
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Pub Dt:
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02/08/2018
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Title:
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SEMICONDUCTOR DEVICE HAVING MULTIPLE THICKNESS OXIDES
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Patent #:
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Issue Dt:
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07/31/2018
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Application #:
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15230871
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Filing Dt:
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08/08/2016
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Publication #:
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Pub Dt:
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02/08/2018
| | | | |
Title:
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PARASITIC CAPACITANCE REDUCING CONTACT STRUCTURE IN A FINFET
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Patent #:
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Issue Dt:
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12/26/2017
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Application #:
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15231087
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Filing Dt:
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08/08/2016
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Title:
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PASSIVATED GERMANIUM-ON-INSULATOR LATERAL BIPOLAR TRANSISTORS
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Patent #:
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Issue Dt:
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04/17/2018
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Application #:
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15231979
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Filing Dt:
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08/09/2016
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Publication #:
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Pub Dt:
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02/15/2018
| | | | |
Title:
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SELF-ALIGNED SINGLE DUMMY FIN CUT WITH TIGHT PITCH
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Patent #:
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Issue Dt:
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09/12/2017
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Application #:
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15236547
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Filing Dt:
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08/15/2016
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Title:
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LATERAL BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE BASE LENGTHS
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Patent #:
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Issue Dt:
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03/06/2018
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Application #:
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15241858
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Filing Dt:
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08/19/2016
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Publication #:
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Pub Dt:
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02/22/2018
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Title:
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WIMPY DEVICE BY SELECTIVE LASER ANNEALING
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Patent #:
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Issue Dt:
|
09/19/2017
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Application #:
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15242045
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Filing Dt:
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08/19/2016
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Title:
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METHOD AND STRUCTURE TO FABRICATE A NANOPOROUS MEMBRANE
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Patent #:
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Issue Dt:
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04/10/2018
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Application #:
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15243052
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Filing Dt:
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08/22/2016
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Publication #:
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Pub Dt:
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02/22/2018
| | | | |
Title:
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DENSE VERTICAL NANOSHEET
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Patent #:
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Issue Dt:
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03/27/2018
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Application #:
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15246797
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Filing Dt:
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08/25/2016
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Publication #:
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Pub Dt:
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03/01/2018
| | | | |
Title:
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VERTICAL FUSE STRUCTURES
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Patent #:
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Issue Dt:
|
04/24/2018
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Application #:
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15251403
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Filing Dt:
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08/30/2016
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Publication #:
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Pub Dt:
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03/01/2018
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Title:
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INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
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08/14/2018
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Application #:
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15251450
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Filing Dt:
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08/30/2016
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Publication #:
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Pub Dt:
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03/01/2018
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Title:
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METAL SILICATE SPACERS FOR FULLY ALIGNED VIAS
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Patent #:
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Issue Dt:
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06/20/2017
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Application #:
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15260441
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Filing Dt:
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09/09/2016
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Title:
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CONDUCTIVE CONTACTS IN SEMICONDUCTOR ON INSULATOR SUBSTRATE
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Patent #:
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Issue Dt:
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06/19/2018
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Application #:
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15261291
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Filing Dt:
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09/09/2016
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Publication #:
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Pub Dt:
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03/15/2018
| | | | |
Title:
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MULTI-ANGLED DEPOSITION AND MASKING FOR CUSTOM SPACER TRIM AND SELECTED SPACER REMOVAL
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Patent #:
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Issue Dt:
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08/29/2017
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Application #:
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15266414
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Filing Dt:
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09/15/2016
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Title:
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INTEGRATED GATE DRIVER
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Patent #:
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Issue Dt:
|
07/24/2018
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Application #:
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15267646
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Filing Dt:
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09/16/2016
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Publication #:
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Pub Dt:
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03/22/2018
| | | | |
Title:
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ASYMMETRIC JUNCTION ENGINEERING FOR NARROW BAND GAP MOSFET
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Patent #:
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Issue Dt:
|
01/02/2018
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Application #:
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15268787
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Filing Dt:
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09/19/2016
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Title:
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SELECTIVE SURFACE MODIFICATION OF INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
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04/18/2017
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Application #:
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15271464
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Filing Dt:
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09/21/2016
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Title:
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III-V COMPOUND SEMICONDUCTOR CHANNEL MATERIAL FORMATION ON MANDREL AFTER MIDDLE-OF-THE-LINE DIELECTRIC FORMATION
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Patent #:
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Issue Dt:
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03/20/2018
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Application #:
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15271939
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Filing Dt:
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09/21/2016
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Publication #:
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Pub Dt:
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03/22/2018
| | | | |
Title:
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THIN LOW DEFECT RELAXED SILICON GERMANIUM LAYERS ON BULK SILICON SUBSTRATES
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Patent #:
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Issue Dt:
|
07/11/2017
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Application #:
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15272811
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Filing Dt:
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09/22/2016
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Title:
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SELF-ALIGNED SPACER FOR CUT-LAST TRANSISTOR FABRICATION
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Patent #:
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Issue Dt:
|
10/31/2017
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Application #:
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15272977
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Filing Dt:
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09/22/2016
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Title:
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SACRIFICIAL CAP FOR FORMING SEMICONDUCTOR CONTACT
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Patent #:
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Issue Dt:
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07/11/2017
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Application #:
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15274621
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Filing Dt:
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09/23/2016
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Title:
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ON-CHIP MIM CAPACITOR
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Patent #:
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Issue Dt:
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08/22/2017
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Application #:
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15275565
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Filing Dt:
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09/26/2016
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Title:
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SIMPLIFIED GATE STACK PROCESS TO IMPROVE DUAL CHANNEL CMOS PERFORMANCE
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Patent #:
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Issue Dt:
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07/11/2017
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Application #:
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15277291
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Filing Dt:
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09/27/2016
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Title:
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SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CARBON NANOTUBE GATE
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Patent #:
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Issue Dt:
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09/05/2017
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Application #:
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15278747
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Filing Dt:
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09/28/2016
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Title:
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HYBRIDIZATION FIN REVEAL FOR UNIFORM FIN REVEAL DEPTH ACROSS DIFFERENT FIN PITCHES
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Patent #:
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Issue Dt:
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10/17/2017
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Application #:
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15280518
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Filing Dt:
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09/29/2016
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Title:
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HETEROGENEOUS METALLIZATION USING SOLID DIFFUSION REMOVAL OF METAL INTERCONNECTS
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Patent #:
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Issue Dt:
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06/27/2017
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Application #:
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15282012
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Filing Dt:
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09/30/2016
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Title:
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VIA AND CHAMFER CONTROL FOR ADVANCED INTERCONNECTS
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Patent #:
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Issue Dt:
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06/13/2017
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Application #:
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15282152
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Filing Dt:
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09/30/2016
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Title:
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CONTACT RESISTANCE REDUCTION BY III-V GA DEFICIENT SURFACE
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Patent #:
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Issue Dt:
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11/21/2017
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Application #:
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15282378
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Filing Dt:
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09/30/2016
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Title:
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SHALLOW TRENCH ISOLATION RECESS PROCESS FLOW FOR VERTICAL FIELD EFFECT TRANSISTOR FABRICATION
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Patent #:
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Issue Dt:
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08/22/2017
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Application #:
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15289374
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Filing Dt:
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10/10/2016
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Title:
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FINFETS WITH CONTROLLABLE AND ADJUSTABLE CHANNEL DOPING
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Patent #:
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Issue Dt:
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10/15/2019
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Application #:
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15292789
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Filing Dt:
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10/13/2016
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Publication #:
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Pub Dt:
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07/06/2017
| | | | |
Title:
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JUNCTIONLESS BACK END OF THE LINE VIA CONTACT
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Patent #:
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Issue Dt:
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08/15/2017
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Application #:
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15293572
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Filing Dt:
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10/14/2016
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Publication #:
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Pub Dt:
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06/22/2017
| | | | |
Title:
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NANOWIRE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/17/2018
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Application #:
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15294467
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Filing Dt:
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10/14/2016
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Publication #:
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Pub Dt:
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04/19/2018
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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12/25/2018
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Application #:
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15294986
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Filing Dt:
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10/17/2016
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Publication #:
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Pub Dt:
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04/19/2018
| | | | |
Title:
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FORMING STRAINED CHANNEL WITH GERMANIUM CONDENSATION
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Patent #:
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Issue Dt:
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08/22/2017
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Application #:
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15298966
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Filing Dt:
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10/20/2016
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Title:
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VERTICAL TRANSISTOR WITH UNIFORM BOTTOM SPACER FORMED BY SELECTIVE OXIDATION
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Patent #:
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Issue Dt:
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01/30/2018
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Application #:
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15334796
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Filing Dt:
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10/26/2016
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Title:
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BARRIER PLANARIZATION FOR INTERCONNECT METALLIZATION
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Patent #:
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Issue Dt:
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05/23/2017
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Application #:
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15336859
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Filing Dt:
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10/28/2016
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Title:
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FORMING SELF-ALIGNED DUAL PATTERNING MANDREL AND NON-MANDREL INTERCONNECTS
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Patent #:
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Issue Dt:
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02/20/2018
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Application #:
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15339164
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Filing Dt:
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10/31/2016
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Title:
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FORMING ON-CHIP METAL-INSULATOR-SEMICONDUCTOR CAPACITOR
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Patent #:
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Issue Dt:
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07/11/2017
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Application #:
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15339402
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Filing Dt:
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10/31/2016
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Title:
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GATE HEIGHT AND SPACER UNIFORMITY
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