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Reel/Frame:045790/0870   Pages: 8
Recorded: 05/12/2018
Attorney Dkt #:TCLBG000
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 18
1
Patent #:
Issue Dt:
04/04/2017
Application #:
14590852
Filing Dt:
01/06/2015
Publication #:
Pub Dt:
03/31/2016
Title:
CROSS-COUPLED THYRISTOR SRAM SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION
2
Patent #:
Issue Dt:
10/04/2016
Application #:
14607023
Filing Dt:
01/27/2015
Publication #:
Pub Dt:
03/31/2016
Title:
TWO-TRANSISTOR THYRISTOR SRAM CIRCUIT AND METHODS OF OPERATION
3
Patent #:
Issue Dt:
02/07/2017
Application #:
14607025
Filing Dt:
01/27/2015
Publication #:
Pub Dt:
03/31/2016
Title:
Two-Transistor SRAM Semiconductor Structure and Methods of Fabrication
4
Patent #:
Issue Dt:
11/15/2016
Application #:
14740186
Filing Dt:
06/15/2015
Publication #:
Pub Dt:
03/31/2016
Title:
SIX-TRANSISTOR THYRISTOR SRAM CIRCUITS AND METHODS OF OPERATION
5
Patent #:
Issue Dt:
02/07/2017
Application #:
14740197
Filing Dt:
06/15/2015
Publication #:
Pub Dt:
03/31/2016
Title:
Six-Transistor SRAM Semiconductor Structures and Methods of Fabrication
6
Patent #:
Issue Dt:
05/07/2019
Application #:
14740209
Filing Dt:
06/15/2015
Publication #:
Pub Dt:
03/31/2016
Title:
WRITE ASSIST THYRISTOR-BASED SRAM CIRCUITS AND METHODS OF OPERATION
7
Patent #:
Issue Dt:
08/21/2018
Application #:
15011396
Filing Dt:
01/29/2016
Publication #:
Pub Dt:
05/26/2016
Title:
CROSS-COUPLED THYRISTOR SRAM SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION
8
Patent #:
Issue Dt:
08/22/2017
Application #:
15216652
Filing Dt:
07/21/2016
Publication #:
Pub Dt:
11/10/2016
Title:
Methods of Reading Six-Transistor Cross-Coupled Thyristor-Based SRAM Memory Cells
9
Patent #:
Issue Dt:
12/12/2017
Application #:
15288874
Filing Dt:
10/07/2016
Title:
SYSTEMS AND METHODS FOR MANAGING READ VOLTAGES IN A CROSS-POINT MEMORY ARRAY
10
Patent #:
Issue Dt:
05/09/2017
Application #:
15288886
Filing Dt:
10/07/2016
Title:
SYSTEMS AND METHODS FOR MANAGING WRITE VOLTAGES IN A CROSS-POINT MEMORY ARRAY
11
Patent #:
Issue Dt:
05/16/2017
Application #:
15288914
Filing Dt:
10/07/2016
Title:
MEMORY ARRAY HAVING SEGMENTED ROW ADDRESSED PAGE REGISTERS
12
Patent #:
Issue Dt:
07/24/2018
Application #:
15289023
Filing Dt:
10/07/2016
Publication #:
Pub Dt:
04/12/2018
Title:
MEMORY DISTURB RECOVERY SCHEME FOR CROSS-POINT MEMORY ARRAYS
13
Patent #:
Issue Dt:
07/10/2018
Application #:
15349978
Filing Dt:
11/11/2016
Publication #:
Pub Dt:
12/07/2017
Title:
Thyristor Memory Cell with Assist Device
14
Patent #:
Issue Dt:
02/20/2018
Application #:
15426588
Filing Dt:
02/07/2017
Publication #:
Pub Dt:
05/25/2017
Title:
Two-Transistor SRAM Semiconductor Structure and Methods of Fabrication
15
Patent #:
Issue Dt:
08/29/2017
Application #:
15426888
Filing Dt:
02/07/2017
Publication #:
Pub Dt:
05/25/2017
Title:
SIX-TRANSISTOR SRAM SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION
16
Patent #:
Issue Dt:
07/10/2018
Application #:
15426909
Filing Dt:
02/07/2017
Publication #:
Pub Dt:
12/28/2017
Title:
Methods of Reading and Writing Data in a Thyristor Random Access Memory
17
Patent #:
Issue Dt:
04/09/2019
Application #:
15426972
Filing Dt:
02/07/2017
Publication #:
Pub Dt:
08/10/2017
Title:
VERTICAL THYRISTOR MEMORY WITH MINORITY CARRIER LIFETIME REDUCTION
18
Patent #:
Issue Dt:
01/14/2020
Application #:
15683760
Filing Dt:
08/22/2017
Publication #:
Pub Dt:
02/22/2018
Title:
HIGH DENSITY VERTICAL THYRISTOR MEMORY CELL ARRAY WITH IMPROVED ISOLATION
Assignor
1
Exec Dt:
01/09/2018
Assignee
1
777 FIRST STREET
PBM #138
GILROY, CALIFORNIA 95020
Correspondence name and address
AKA CHAN LLP / GARY T. AKA
900 LAFAYETTE STREET ST STE 710
SANTA CLARA, CA 95050

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