skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:030770/0876   Pages: 7
Recorded: 07/10/2013
Attorney Dkt #:MEGIKA ASSIGNMENT 092968
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
7282804
Issue Dt:
10/16/2007
Application #:
10614928
Filing Dt:
07/08/2003
Publication #:
US20040023436
Pub Dt:
02/05/2004
Title:
STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD
2
Patent #:
RE43674
Issue Dt:
09/18/2012
Application #:
11518595
Filing Dt:
09/08/2006
Title:
POST PASSIVATION METAL SCHEME FOR HIGH-PERFORMANCE INTEGRATED CIRCUIT DEVICES
3
Patent #:
NONE
Issue Dt:
Application #:
11678597
Filing Dt:
02/25/2007
Publication #:
US20070164412
Pub Dt:
07/19/2007
Title:
METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT
4
Patent #:
7521812
Issue Dt:
04/21/2009
Application #:
11678598
Filing Dt:
02/25/2007
Publication #:
US20070164452
Pub Dt:
07/19/2007
Title:
METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT
5
Patent #:
9153555
Issue Dt:
10/06/2015
Application #:
11678599
Filing Dt:
02/25/2007
Publication #:
US20070164453
Pub Dt:
07/19/2007
Title:
METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT
6
Patent #:
8742580
Issue Dt:
06/03/2014
Application #:
11678600
Filing Dt:
02/25/2007
Publication #:
US20070164441
Pub Dt:
07/19/2007
Title:
METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT
7
Patent #:
8026588
Issue Dt:
09/27/2011
Application #:
11707827
Filing Dt:
02/16/2007
Publication #:
US20070273031
Pub Dt:
11/29/2007
Title:
METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT
8
Patent #:
7459790
Issue Dt:
12/02/2008
Application #:
11788221
Filing Dt:
04/19/2007
Publication #:
US20070200244
Pub Dt:
08/30/2007
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
9
Patent #:
7417317
Issue Dt:
08/26/2008
Application #:
11818028
Filing Dt:
06/13/2007
Publication #:
US20070246834
Pub Dt:
10/25/2007
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
10
Patent #:
NONE
Issue Dt:
Application #:
11877641
Filing Dt:
10/23/2007
Publication #:
US20080042238
Pub Dt:
02/21/2008
Title:
HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS
11
Patent #:
7422941
Issue Dt:
09/09/2008
Application #:
11877647
Filing Dt:
10/23/2007
Publication #:
US20080044976
Pub Dt:
02/21/2008
Title:
HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS
12
Patent #:
NONE
Issue Dt:
Application #:
11877652
Filing Dt:
10/23/2007
Publication #:
US20080044977
Pub Dt:
02/21/2008
Title:
High performance system-on-chip using post passivation process
13
Patent #:
NONE
Issue Dt:
Application #:
11877654
Filing Dt:
10/23/2007
Publication #:
US20080042289
Pub Dt:
02/21/2008
Title:
HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS
14
Patent #:
7482268
Issue Dt:
01/27/2009
Application #:
11877657
Filing Dt:
10/23/2007
Publication #:
US20080045007
Pub Dt:
02/21/2008
Title:
TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS
15
Patent #:
7449752
Issue Dt:
11/11/2008
Application #:
11906833
Filing Dt:
10/04/2007
Publication #:
US20080029785
Pub Dt:
02/07/2008
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
16
Patent #:
7902067
Issue Dt:
03/08/2011
Application #:
11906840
Filing Dt:
10/04/2007
Publication #:
US20080032496
Pub Dt:
02/07/2008
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
17
Patent #:
8138079
Issue Dt:
03/20/2012
Application #:
11926154
Filing Dt:
10/29/2007
Publication #:
US20080233733
Pub Dt:
09/25/2008
Title:
METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT
18
Patent #:
9142527
Issue Dt:
09/22/2015
Application #:
11926156
Filing Dt:
10/29/2007
Publication #:
US20080045003
Pub Dt:
02/21/2008
Title:
METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT
19
Patent #:
8481418
Issue Dt:
07/09/2013
Application #:
11930220
Filing Dt:
10/31/2007
Publication #:
US20090137110
Pub Dt:
05/28/2009
Title:
LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE
20
Patent #:
7427560
Issue Dt:
09/23/2008
Application #:
11930682
Filing Dt:
10/31/2007
Publication #:
US20080050909
Pub Dt:
02/28/2008
Title:
TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S
21
Patent #:
NONE
Issue Dt:
Application #:
11957509
Filing Dt:
12/17/2007
Publication #:
US20080111243
Pub Dt:
05/15/2008
Title:
HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS
22
Patent #:
NONE
Issue Dt:
Application #:
11957510
Filing Dt:
12/17/2007
Publication #:
US20080093745
Pub Dt:
04/24/2008
Title:
High performance system-on-chip using post passivation process
23
Patent #:
8158508
Issue Dt:
04/17/2012
Application #:
11981125
Filing Dt:
10/31/2007
Publication #:
US20080088019
Pub Dt:
04/17/2008
Title:
STRUCTURE AND MANUFACTURING METHOD OF A CHIP SCALE PACKAGE
24
Patent #:
7902679
Issue Dt:
03/08/2011
Application #:
11981138
Filing Dt:
10/31/2007
Publication #:
US20080067677
Pub Dt:
03/20/2008
Title:
A STRUCTURE AND MANUFACTURING METHOD OF A CHIP SCALE PACKAGE WITH LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP
25
Patent #:
8304907
Issue Dt:
11/06/2012
Application #:
12001676
Filing Dt:
12/12/2007
Publication #:
US20080121943
Pub Dt:
05/29/2008
Title:
TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS
26
Patent #:
7535102
Issue Dt:
05/19/2009
Application #:
12098467
Filing Dt:
04/07/2008
Publication #:
US20080185586
Pub Dt:
08/07/2008
Title:
HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY
27
Patent #:
8013449
Issue Dt:
09/06/2011
Application #:
12142825
Filing Dt:
06/20/2008
Publication #:
US20080251924
Pub Dt:
10/16/2008
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
28
Patent #:
8901733
Issue Dt:
12/02/2014
Application #:
12182145
Filing Dt:
07/30/2008
Publication #:
US20110291259
Pub Dt:
12/01/2011
Title:
RELIABLE METAL BUMPS ON TOP OF I/O PADS AFTER REMOVAL OF TEST PROBE MARKS
29
Patent #:
8120181
Issue Dt:
02/21/2012
Application #:
12182148
Filing Dt:
07/30/2008
Publication #:
US20080290520
Pub Dt:
11/27/2008
Title:
POST PASSIVATION INTERCONNECTION PROCESS AND STRUCTURES
30
Patent #:
9018774
Issue Dt:
04/28/2015
Application #:
12206751
Filing Dt:
09/09/2008
Publication #:
US20090008778
Pub Dt:
01/08/2009
Title:
CHIP PACKAGE
31
Patent #:
7880304
Issue Dt:
02/01/2011
Application #:
12370617
Filing Dt:
02/13/2009
Publication #:
US20090146305
Pub Dt:
06/11/2009
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
32
Patent #:
8072070
Issue Dt:
12/06/2011
Application #:
12493258
Filing Dt:
06/29/2009
Publication #:
US20090261473
Pub Dt:
10/22/2009
Title:
LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP
33
Patent #:
8334588
Issue Dt:
12/18/2012
Application #:
13098340
Filing Dt:
04/29/2011
Publication #:
US20110204522
Pub Dt:
08/25/2011
Title:
CIRCUIT COMPONENT WITH CONDUCTIVE LAYER STRUCTURE
34
Patent #:
8519552
Issue Dt:
08/27/2013
Application #:
13207346
Filing Dt:
08/10/2011
Publication #:
US20110291272
Pub Dt:
12/01/2011
Title:
CHIP STRUCTURE
35
Patent #:
NONE
Issue Dt:
Application #:
13735894
Filing Dt:
01/07/2013
Publication #:
US20140021630
Pub Dt:
01/23/2014
Title:
HIGH PERFORMANCE IC CHIP HAVING DISCRETE DECOUPLING CAPACITORS ATTACHED TO ITS IC SURFACE
Assignor
1
MEGICA CORPORATION
Exec Dt:
04/28/2006
Assignee
1
MEGICA CORPORATION
ROOM 301/302, NO 47, PARK 2ND RD.
SCIENCE-BASED INDUSTRIAL PARK
HSINCHU, TAIWAN ROC
Correspondence name and address
QUALCOMM INCORPORATED
5775 MOREHOUSE DRIVE
SAN DIEGO, CA 92121-1714

Search Results as of: 05/31/2024 11:07 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT