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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09347203
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Filing Dt:
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07/02/1999
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Title:
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SPLIT GATE FLASH MEMORY CELL
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09350964
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Filing Dt:
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07/09/1999
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Title:
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DEVICE AND METHOD FOR PLANARIZING A THIN FILM
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09354622
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Filing Dt:
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07/15/1999
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Title:
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METHOD OF REDUCING CMP DISHING EFFECT
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09358761
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Filing Dt:
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07/22/1999
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Title:
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METHOD OF MANUFACTURING A CAPACITOR FOR HIGH DENSITY DRAMS
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09358762
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Filing Dt:
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07/22/1999
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Title:
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METHOD OF FORMING A NOVEL SELF-ALIGNED OFFSET THIN FILM TRANSISTOR AND THE STRUCTURE OF THE SAME
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09359414
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Filing Dt:
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07/23/1999
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Title:
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METHOD OF FORMING DUAL DAMASCENE STRUCTURES
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09359415
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Filing Dt:
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07/23/1999
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Title:
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A METHOD OF FORMING A SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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10/10/2000
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Application #:
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09360809
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Filing Dt:
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07/26/1999
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Title:
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NOVEL VERTICAL POLY LOAD DEVICE IN 4T SRAM TECHNOLOGY
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09362916
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Filing Dt:
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07/27/1999
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Title:
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CURRENT SOURCE USING MERGED VERTICAL BIPOLAR TRANSISTOR ON GATE INDUCED GATE LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09365186
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Filing Dt:
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08/02/1999
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Title:
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ELECTROSTATIC DISCHARGE PROTETION DEVICE WITH RESISTIVE DRAIN STRUCTURE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09365436
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Filing Dt:
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08/02/1999
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Publication #:
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Pub Dt:
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08/16/2001
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Title:
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VERTICAL BIPOLAR TRANSISTOR BASED ON GATE INDUCED DRAIN LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09365732
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Filing Dt:
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08/03/1999
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Title:
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EPROM CELL STRUCTURE AND A METHOD FOR FORMING THE EPROM CELL STRUCTURE
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09365733
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Filing Dt:
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08/03/1999
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Title:
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METHOD FOR FORMING A FLASH MEMORY CELL WITH IMPROVED DRAIN ERASE PERFORMANCE
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09371728
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Filing Dt:
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08/10/1999
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Title:
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STRUCTURE AND FABRICATION METHOD FOR MULTIPLE CROWN CAPACITOR
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09373318
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Filing Dt:
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08/12/1999
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Title:
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SSELF-ALIGNED EETCHING PROCESS
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09375519
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Filing Dt:
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08/17/1999
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Title:
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METHOD TO FABRICATE DRAM CAPACITOR USING DAMASCENCE PROCESSES
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Patent #:
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Issue Dt:
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01/15/2002
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Application #:
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09376481
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Filing Dt:
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08/18/1999
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Title:
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METHOD TO FABRICATE EMBEDDED DRAM WITH SALICIDE LOGIC CELL STRUCTURE
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09378044
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Filing Dt:
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08/20/1999
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Title:
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METHOD OF FORMING A SINGLE POLY CYLINDRICAL FLASH MEMORY CELL HAVING HIGH COUPLING RATIO
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09378271
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Filing Dt:
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08/20/1999
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Title:
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SOURCE SIDE INJECTION FLASH EEPROM MEMORY CELL AND OPERATION
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09378558
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Filing Dt:
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08/19/1999
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Title:
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ONE TRANSISTOR EEPROM CELL USING FERRO-ELECTRIC SPACER
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09382078
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Filing Dt:
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08/24/1999
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Title:
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METHOD FOR PROGRAMMING AND ERASING A TRIPLE-POLY SPLIT-GATE FLASH MEMORY
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09384013
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Filing Dt:
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08/26/1999
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Title:
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METHOD OF FABRICATING REDUCED CRITICAL DIMENSION FOR CONDUCTIVE LINE AND SPACE
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09387506
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Filing Dt:
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09/01/1999
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Title:
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METHOD FOR FORMING INTER-METAL DIELECTRIC LAYERS IN METALLIZATION PROCESS
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09387730
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Filing Dt:
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09/01/1999
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Title:
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METHOD FOR FORMING BOTTOM ANTI-REFLECTIVE COATING (BARC)
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09391496
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Filing Dt:
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09/08/1999
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Title:
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METHOD FOR IMPROVING THE THERMAL CONDUCTIVITY OF METAL LINES IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09392158
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Filing Dt:
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09/08/1999
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Title:
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PROCESS OF PLANARIZING CROWN CAPACITOR FOR INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
10/16/2001
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Application #:
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09393610
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Filing Dt:
|
09/10/1999
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Title:
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METHOD OF FABRICATING BIT LINES
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Patent #:
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Issue Dt:
|
03/13/2001
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Application #:
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09393705
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Filing Dt:
|
09/10/1999
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|
Title:
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METHOD TO FABRICATE DRAM CAPACITOR
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Patent #:
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|
Issue Dt:
|
07/10/2001
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Application #:
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09393983
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Filing Dt:
|
09/10/1999
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Title:
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FABRICATION METHOD OF A DEVICE ISOLATION STRUCTURE
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Patent #:
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|
Issue Dt:
|
05/15/2001
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Application #:
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09394270
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Filing Dt:
|
09/10/1999
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Title:
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METHOD OF MANUFACTURING FLOATING GATE OF STACKED-GATE NONVOLATILE MEMORY UNIT
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Patent #:
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Issue Dt:
|
09/18/2001
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Application #:
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09395108
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Filing Dt:
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09/14/1999
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Title:
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METHOD FOR FORMING PULLBACK OPENING ABOVE SHALLOW TRENC ISOLATION STRUCTURE
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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09395109
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Filing Dt:
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09/14/1999
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Title:
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METHOD OF FABRICATING TRANSISTOR HAVING A METAL GATE AND A GATE
DIELECTRIC LAYER WITH A HIGH DIELECTRIC CONTSTANT
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09395110
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Filing Dt:
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09/14/1999
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Title:
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METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE
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Patent #:
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Issue Dt:
|
05/01/2001
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Application #:
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09395111
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Filing Dt:
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09/14/1999
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Title:
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METHOD FOR FORMING CONTACT PLUG
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Patent #:
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Issue Dt:
|
08/07/2001
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Application #:
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09395187
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Filing Dt:
|
09/14/1999
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Title:
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METHOD OF FORMING A DRAM CROWN CAPACITOR
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Patent #:
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Issue Dt:
|
08/28/2001
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Application #:
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09395188
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Filing Dt:
|
09/14/1999
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Title:
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METHOD FOR FABRICATING AN EMBEDDED FLASH MEMORY CELL
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Patent #:
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|
Issue Dt:
|
01/09/2001
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Application #:
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09395428
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Filing Dt:
|
09/14/1999
|
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Title:
|
METHOD OF FABRICATING SHALLOW TRENCH INSOLATION
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Patent #:
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Issue Dt:
|
04/03/2001
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Application #:
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09400626
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Filing Dt:
|
09/20/1999
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Title:
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INTERCONNECTION LINES FOR IMPROVING THERMAL CONDUCTIVITY IN INTEGRATED CIRCUITS AND METHOD FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
|
08/07/2001
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Application #:
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09406728
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Filing Dt:
|
09/28/1999
|
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Title:
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METHOD FOR FORMING A CAPACITOR OF A DRAM CELL
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Patent #:
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Issue Dt:
|
11/07/2000
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Application #:
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09411133
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Filing Dt:
|
10/01/1999
|
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Title:
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METHOD FOR FORMING FLASH MEMORY F ETOX-CELL PROGRAMMED BY BAND-TO-BAND TUNNELING INDUCED SUBSTRATE HOT ELECTRON AND READ BY GATE INDUCED DRAIN LEAKAGE CURRENT
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Patent #:
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Issue Dt:
|
06/05/2001
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Application #:
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09414252
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Filing Dt:
|
10/07/1999
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Title:
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FABRICATION METHOD FOR A BORDERLESS VIA OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
07/16/2002
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Application #:
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09414281
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Filing Dt:
|
10/07/1999
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|
Title:
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METHOD OF FORMING SELF-ALIGNED MASK ROM
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|
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Patent #:
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Issue Dt:
|
07/02/2002
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Application #:
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09414817
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Filing Dt:
|
10/08/1999
|
|
Title:
|
METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE
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|
|
|
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Patent #:
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|
Issue Dt:
|
07/03/2001
|
Application #:
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09417357
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Filing Dt:
|
10/13/1999
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|
Title:
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PRE-TREATMENT FOR SALICIDE PROCESS
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Patent #:
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Issue Dt:
|
11/14/2000
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Application #:
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09417393
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Filing Dt:
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10/13/1999
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|
Title:
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METHOD OF FABRICATING A FLASH MEMORY
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Patent #:
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|
Issue Dt:
|
05/01/2001
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Application #:
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09418833
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Filing Dt:
|
10/15/1999
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Title:
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SINGLE POLY EPLD CELL AND ITS FABRICATING METHOD
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Patent #:
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Issue Dt:
|
01/16/2001
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Application #:
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09419402
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Filing Dt:
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10/14/1999
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Title:
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METHOD FOR FORMING A CROWN CAPACITOR HAVING HSG FOR DRAM MEMORY
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Patent #:
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Issue Dt:
|
12/12/2000
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Application #:
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09422050
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Filing Dt:
|
10/20/1999
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Title:
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METHOD FOR OPERATION OF A FLASH MEMORY USING N+/P- WELL DIODE
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Patent #:
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Issue Dt:
|
07/17/2001
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Application #:
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09422051
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Filing Dt:
|
10/20/1999
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Title:
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SINGLE POLYSILICON DRAM CELL AND ARRAY WITH CURRENT GAIN
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Patent #:
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Issue Dt:
|
03/27/2001
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Application #:
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09427438
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Filing Dt:
|
10/26/1999
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Title:
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MULTI-LEVEL FLASH MEMORY USING TRIPLE WELL PROCESS AND METHOD OF MAKING
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09429190
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Filing Dt:
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10/28/1999
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Title:
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METHOD FOR FORMING INTERLAYER DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09429601
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Filing Dt:
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10/28/1999
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Title:
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DUAL-DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09430749
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Filing Dt:
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10/29/1999
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Title:
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METHOD AND STRUCTURE FOR A CONDUCTIVE AND A DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09439988
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Filing Dt:
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11/15/1999
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Title:
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DYNAMIC RANDOM ACCESS MEMORY WITH SLANTED ACTIVE REGIONS
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Patent #:
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Issue Dt:
|
06/05/2001
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Application #:
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09440138
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Filing Dt:
|
11/15/1999
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Title:
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NONVOLATILE MEMORIES WITH HIGH CAPACITIVE-COUPLING RATIO
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Patent #:
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Issue Dt:
|
09/25/2001
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Application #:
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09440902
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Filing Dt:
|
11/16/1999
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Title:
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METHOD OF MANUFACTURING CROWN-SHAPED DRAM CAPACITOR
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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09440904
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Filing Dt:
|
11/16/1999
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Publication #:
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Pub Dt:
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06/06/2002
| | | | |
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Title:
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METHOD OF PLANARIZING POLYSILLICON PLUG
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Patent #:
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Issue Dt:
|
06/26/2001
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Application #:
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09448018
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Filing Dt:
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11/23/1999
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Title:
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METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE
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Patent #:
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Issue Dt:
|
05/22/2001
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Application #:
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09451384
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Filing Dt:
|
11/30/1999
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Title:
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METHOD FOR MANUFACTURING STACKED CAPACITOR
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Patent #:
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Issue Dt:
|
11/12/2002
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Application #:
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09451853
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Filing Dt:
|
12/01/1999
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Title:
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METHOD OF FORMING A DUAL-LAYER ANTI-REFLECTIVE COATING
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Patent #:
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Issue Dt:
|
06/12/2001
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Application #:
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09454387
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Filing Dt:
|
12/03/1999
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Title:
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FABRICATION METHOD FOR A DOUBLE-SIDE DOUBLE-CROWN STACKED CAPACITOR
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Patent #:
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Issue Dt:
|
01/30/2001
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Application #:
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09454490
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Filing Dt:
|
12/02/1999
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Title:
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FLASH MEMORY CELL USING P+/N-WELL DIODE WITH DOUBLE POLY FLOATING GATE
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Patent #:
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Issue Dt:
|
06/25/2002
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Application #:
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09458827
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Filing Dt:
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12/13/1999
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Title:
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AUTO SLURRY DELIVER FINE-TUNE SYSTEM FOR CHEMICAL-MECHANICAL-POLISHING PROCESS AND METHOD OF USING THE SYSTEM
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Patent #:
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Issue Dt:
|
06/12/2001
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Application #:
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09465905
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Filing Dt:
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12/17/1999
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Title:
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METHOD OF FORMING VIA
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09466044
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Filing Dt:
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12/17/1999
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Title:
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METHOD OF MANUFACTURING DOUBLE-RECESS CROWN-SHAPED DRAM CAPACITOR
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09468196
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Filing Dt:
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12/21/1999
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Title:
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SELF-ALIGNED CONTACT PROCESS
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09482421
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Filing Dt:
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01/13/2000
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Title:
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Process For Forming A Borderless Via In A Semiconductor Device
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09482757
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Filing Dt:
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01/13/2000
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Title:
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Method Of Fabricating Transistor
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Patent #:
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Issue Dt:
|
10/17/2000
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Application #:
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09488955
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Filing Dt:
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01/21/2000
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Title:
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Method of forming crown-shaped capacitor
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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09490275
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Filing Dt:
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01/24/2000
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Title:
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Method of forming shallow trench isolation structures
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Patent #:
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Issue Dt:
|
03/26/2002
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Application #:
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09491067
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Filing Dt:
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01/25/2000
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Title:
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Method of forming pattern
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09494524
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Filing Dt:
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01/31/2000
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Title:
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SELF-ALIGNED FABRICATING PROCESS AND STRUCTURE OF SOURCE LINE OF ETOX FLASH MEMORY
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09498329
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Filing Dt:
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02/04/2000
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Title:
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Method of fabricating integrated circuits
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09499067
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Filing Dt:
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02/04/2000
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Title:
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Copper damascene manufacturing process
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09513268
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Filing Dt:
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02/24/2000
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Title:
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Method of forming T-shaped gate
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09515017
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Filing Dt:
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02/29/2000
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Title:
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Method for forming an epitaxial silicon-germanium layer
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09515119
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Filing Dt:
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02/29/2000
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Title:
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Method of fabricating capacitors and devices in mixed-signal integrated circuit
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09515302
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Filing Dt:
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02/29/2000
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Title:
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Self-aligned process for forming source line of etox flash memory
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09515953
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Filing Dt:
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02/29/2000
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Title:
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Method of fabricating a mask ROM
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09521085
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Filing Dt:
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03/07/2000
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Title:
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Damascene local interconnect process
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09525005
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Filing Dt:
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03/14/2000
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Title:
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Multi-zone conditioner for chemical mechanical polishing system
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09528645
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Filing Dt:
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03/20/2000
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Title:
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Method of fabricating intrerconnects
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09534171
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Filing Dt:
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03/24/2000
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Title:
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METHOD FOR FORMING AN ATTENUATED PHASE-SHIFTING MASK
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09535494
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Filing Dt:
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03/24/2000
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Title:
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METHOD OF FABRICATING COPPER DAMASCENE THAT PREVENTS FORMATION OF DISHING PITS
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09535509
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Filing Dt:
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03/24/2000
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Title:
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Bonding pad structure and manufacturing method thereof
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09538911
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Filing Dt:
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03/30/2000
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Title:
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PROCESS FOR FABRICATING CAPACITOR
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09545038
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Filing Dt:
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04/07/2000
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Title:
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Method for reading 2-bit etox-cells using gate induced drain leakage current
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09557510
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Filing Dt:
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04/25/2000
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Title:
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Method of fabricating dual damascene structure
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09568495
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Filing Dt:
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05/11/2000
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Title:
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Method of doing ESD protective device ion implant without additional photo mask
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