Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 029153/0882 | |
| Pages: | 9 |
| | Recorded: | 10/18/2012 | | |
| Attorney Dkt #: | IMEC821.001AUS |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13587733
|
Filing Dt:
|
08/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
|
Title:
|
TUNNEL TRANSISTOR, LOGICAL GATE INCLUDING THE TRANSISTOR, STATIC RANDOM-ACCESS MEMORY USING THE LOGICAL GATE AND METHOD FOR MAKING SUCH A TUNNEL TRANSISTOR
|
|
|
Assignees
|
|
|
|
|
| KAPELDREEF 75 |
| LEUVEN, BELGIUM 3001 |
|
|
|
|
|
| WAAISTRAAT 6 - BOX 5105 |
| LEUVEN, BELGIUM 3000 |
|
|
Correspondence name and address
|
| |
ROSE M. THIESSEN
|
| |
2040 MAIN STREET, 14TH FLOOR
|
| |
IRVINE, CA 92614
|
Search Results as of:
05/29/2024 11:15 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
