Total properties:
180
Page
1
of
2
Pages:
1 2
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
09822783
|
Filing Dt:
|
03/30/2001
|
|
Title:
|
MECHANISM FOR EXTENDING PROPERTIES OF VIRTUAL MEMORY PAGES BY A TLB
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
|
09905180
|
Filing Dt:
|
07/13/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
MECHANISM FOR PROGRAMMABLE MODIFICATION OF MEMORY MAPPING GRANULARITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
09921377
|
Filing Dt:
|
08/02/2001
|
|
Title:
|
READ-ONLY ACCESS TO CPO REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
09921400
|
Filing Dt:
|
08/02/2001
|
|
Title:
|
ATOMIC UPDATE OF CPO STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
09977089
|
Filing Dt:
|
10/12/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
CONFIGURABLE PRIORITIZATION OF CORE GENERATED INTERRUPTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
10238993
|
Filing Dt:
|
09/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CLEARING HAZARDS USING JUMP INSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
10279210
|
Filing Dt:
|
10/22/2002
|
|
Title:
|
INSTRUCTION ENCODING FOR SYSTEM REGISTER BIT SET AND CLEAR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
10468434
|
Filing Dt:
|
09/21/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
ADJUSTING THREAD INSTRUCTION ISSUE RATE BASED ON DEVIATION OF ACTUAL EXECUTED NUMBER FROM INTENDED RATE CUMULATIVE NUMBER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
10684350
|
Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
MECHANISMS FOR ASSURING QUALITY OF SERVICE FOR PROGRAMS EXECUTING ON A MULTITHREADED PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2010
|
Application #:
|
10783960
|
Filing Dt:
|
02/20/2004
|
|
Title:
|
METHOD AND APPARATUS FOR GLOBAL ORDERING TO INSURE LATENCY INDEPENDENT COHERENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2009
|
Application #:
|
10928746
|
Filing Dt:
|
08/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
|
Title:
|
APPARATUS, METHOD, AND INSTRUCTION FOR INITIATION OF CONCURRENT INSTRUCTION STREAMS IN A MULTITHREADING MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
10929097
|
Filing Dt:
|
08/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/27/2005
| | | | |
|
Title:
|
APPARATUS, METHOD, AND INSTRUCTION FOR SOFTWARE MANAGEMENT OF MULTIPLE COMPUTATIONAL CONTEXTS IN A MULTITHREADED MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
10929102
|
Filing Dt:
|
08/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
MECHANISMS FOR DYNAMIC CONFIGURATION OF VIRTUAL PROCESSOR RESOURCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
10929342
|
Filing Dt:
|
08/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
INTEGRATED MECHANISM FOR SUSPENSION AND DEALLOCATION OF COMPUTATIONAL THREADS OF EXECUTION IN A PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
10949958
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR DYNAMIC ALLOCATION OF RESOURCES TO EXECUTING THREADS IN A MULTI-THREADED PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
10954988
|
Filing Dt:
|
09/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
|
Title:
|
SYNCHRONIZED STORAGE PROVIDING MULTIPLE SYNCHRONIZATION SEMANTICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2009
|
Application #:
|
10955231
|
Filing Dt:
|
09/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
SMART MEMORY BASED SYNCHRONIZATION CONTROLLER FOR A MULTI-THREADED MULTIPROCESSOR SOC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
11051978
|
Filing Dt:
|
02/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
|
Title:
|
INSTRUCTION/SKID BUFFERS IN A MULTITHREADING MICROPROCESSOR THAT STORE DISPATCHED INSTRUCTIONS TO AVOID RE-FETCHING FLUSHED INSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
11051979
|
Filing Dt:
|
02/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
|
Title:
|
MULTITHREADING MICROPROCESSOR WITH OPTIMIZED THREAD SCHEDULER FOR INCREASING PIPELINE UTILIZATION EFFICIENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
11051997
|
Filing Dt:
|
02/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
|
Title:
|
INTERFACING EXTERNAL THREAD PRIORITIZING POLICY ENFORCING LOGIC WITH CUSTOMER MODIFIABLE REGISTER TO PROCESSOR INTERNAL SCHEDULER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2009
|
Application #:
|
11075041
|
Filing Dt:
|
03/08/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
|
Title:
|
THREE-TIERED TRANSLATION LOOKASIDE BUFFER HIERARCHY IN A MULTITHREADING MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
11284069
|
Filing Dt:
|
11/21/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CLEARING HAZARDS USING JUMP INSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
11313272
|
Filing Dt:
|
12/20/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
|
Title:
|
SOFTWARE EMULATION OF DIRECTED EXCEPTIONS IN A MULTITHREADING PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
11313296
|
Filing Dt:
|
12/20/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
|
Title:
|
PREEMPTIVE MULTITASKING EMPLOYING SOFTWARE EMULATION OF DIRECTED EXCEPTIONS IN A MULTITHREADING PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2008
|
Application #:
|
11330914
|
Filing Dt:
|
01/11/2006
|
|
Publication #:
|
|
Pub Dt:
|
02/22/2007
| | | | |
|
Title:
|
SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
11330915
|
Filing Dt:
|
01/11/2006
|
|
Publication #:
|
|
Pub Dt:
|
02/22/2007
| | | | |
|
Title:
|
SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
11330916
|
Filing Dt:
|
01/11/2006
|
|
Publication #:
|
|
Pub Dt:
|
02/22/2007
| | | | |
|
Title:
|
SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
11388484
|
Filing Dt:
|
03/23/2006
|
|
Title:
|
User interface for facilitation of high level generation of processor extensions
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
11524822
|
Filing Dt:
|
09/21/2006
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
|
Title:
|
THREAD INSTRUCTION ISSUE POOL COUNTER DECREMENTED UPON EXECUTION AND INCREMENTED AT DESIRED ISSUE RATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
11567290
|
Filing Dt:
|
12/06/2006
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
|
Title:
|
INSTRUCTION ENCODING FOR SYSTEM REGISTER BIT SET AND CLEAR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
11615960
|
Filing Dt:
|
12/23/2006
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2007
| | | | |
|
Title:
|
SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
11615963
|
Filing Dt:
|
12/23/2006
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2007
| | | | |
|
Title:
|
SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
11615964
|
Filing Dt:
|
12/23/2006
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2007
| | | | |
|
Title:
|
SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11615965
|
Filing Dt:
|
12/23/2006
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2007
| | | | |
|
Title:
|
SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2009
|
Application #:
|
11632567
|
Filing Dt:
|
01/11/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
MICROPROCESSOR OUTPUT PORTS AND CONTROL OF INSTRUCTIONS PROVIDED THEREFROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11681610
|
Filing Dt:
|
03/02/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2008
| | | | |
|
Title:
|
HORIZONTALLY-SHARED CACHE VICTIMS IN MULTIPLE CORE PROCESSORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
11725631
|
Filing Dt:
|
03/20/2007
|
|
Publication #:
|
|
Pub Dt:
|
12/13/2007
| | | | |
|
Title:
|
EXPANDED FUNCTIONALITY OF PROCESSOR OPERATIONS WITHIN A FIXED WIDTH INSTRUCTION ENCODING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11767247
|
Filing Dt:
|
06/22/2007
|
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
|
Title:
|
AVOIDING LIVELOCK USING A CACHE MANAGER IN MULTIPLE CORE PROCESSORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11949603
|
Filing Dt:
|
12/03/2007
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2008
| | | | |
|
Title:
|
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONDITIONALLY SUSPENDING ISSUING INSTRUCTIONS OF A THREAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2016
|
Application #:
|
12322942
|
Filing Dt:
|
02/09/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/20/2009
| | | | |
|
Title:
|
Prioritising of instruction fetching in microprocessor systems
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
12383118
|
Filing Dt:
|
03/19/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
|
Title:
|
Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
12387152
|
Filing Dt:
|
04/28/2009
|
|
Publication #:
|
|
Pub Dt:
|
11/19/2009
| | | | |
|
Title:
|
SYSTEM FOR PROVIDING TRACE DATA IN A DATA PROCESSOR HAVING A PIPELINED ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
12495375
|
Filing Dt:
|
06/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
THREE-TIERED TRANSLATION LOOKASIDE BUFFER HIERARCHY IN A MULTITHREADING MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12557421
|
Filing Dt:
|
09/10/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR GLOBAL ORDERING TO INSURE LATENCY INDEPENDENT COHERENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2012
|
Application #:
|
12576942
|
Filing Dt:
|
10/09/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/04/2010
| | | | |
|
Title:
|
INSTRUCTION ENCODING FOR SYSTEM REGISTER BIT SET AND CLEAR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
12584759
|
Filing Dt:
|
09/11/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/28/2010
| | | | |
|
Title:
|
Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12586649
|
Filing Dt:
|
09/25/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ENSURING DATA CACHE COHERENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2012
|
Application #:
|
12605201
|
Filing Dt:
|
10/23/2009
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2010
| | | | |
|
Title:
|
APPARATUS, METHOD AND INSTRUCTION FOR INITIATION OF CONCURRENT INSTRUCTION STREAMS IN A MULTITHREADING MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12684564
|
Filing Dt:
|
01/08/2010
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2010
| | | | |
|
Title:
|
MULTITHREADING MICROPROCESSOR WITH OPTIMIZED THREAD SCHEDULER FOR INCREASING PIPELINE UTILIZATION EFFICIENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
12828056
|
Filing Dt:
|
06/30/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2011
| | | | |
|
Title:
|
HORIZONTALLY-SHARED CACHE VICTIMS IN MULTIPLE CORE PROCESSORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12891503
|
Filing Dt:
|
09/27/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/29/2012
| | | | |
|
Title:
|
MICROPROCESSOR WITH DUAL-LEVEL ADDRESS TRANSLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
12891530
|
Filing Dt:
|
09/27/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/29/2012
| | | | |
|
Title:
|
MICROPROCESSOR SYSTEM FOR VIRTUAL MACHINE EXECUTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12911901
|
Filing Dt:
|
10/26/2010
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2011
| | | | |
|
Title:
|
SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2017
|
Application #:
|
13138176
|
Filing Dt:
|
09/20/2011
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
|
Title:
|
SCHEDULING EXECUTION OF INSTRUCTIONS ON A PROCESSOR HAVING MULTIPLE HARDWARE THREADS WITH DIFFERENT EXECUTION RESOURCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13436654
|
Filing Dt:
|
03/30/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
|
Title:
|
Apparatus and Method for Guest and Root Register Sharing in a Virtual Machine
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2020
|
Application #:
|
13491781
|
Filing Dt:
|
06/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
Rescheduling Threads Using Different Cores In A Multithreaded Microprocessor Having A Shared Register Pool
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2015
|
Application #:
|
13555894
|
Filing Dt:
|
07/23/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ENSURING DATA CACHE COHERENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2015
|
Application #:
|
13563025
|
Filing Dt:
|
07/31/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
|
Title:
|
RESTORING A REGISTER RENAMING MAP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2016
|
Application #:
|
13683875
|
Filing Dt:
|
11/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
|
Title:
|
Processor with Kernel Mode Access to User Space Virtual Addresses
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2015
|
Application #:
|
13772759
|
Filing Dt:
|
02/21/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
|
Title:
|
MULTI-THRESHOLD FLASH NCL CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13780115
|
Filing Dt:
|
02/28/2013
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
GLOBAL REGISTER PROTECTION IN A MULTI-THREADED PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2015
|
Application #:
|
13780197
|
Filing Dt:
|
02/28/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
|
Title:
|
RESOURCE SHARING USING PROCESS DELAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2017
|
Application #:
|
13781319
|
Filing Dt:
|
02/28/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
|
Title:
|
Way Lookahead
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
13789443
|
Filing Dt:
|
03/07/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
|
Title:
|
Apparatus and Method for Operating a Processor with an Operation Cache
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2020
|
Application #:
|
13789467
|
Filing Dt:
|
03/07/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
|
Title:
|
Apparatus and Method for Bonding Branch Instruction with Architectural Delay Slot
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
13827902
|
Filing Dt:
|
03/14/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
|
Title:
|
SELF-READY FLASH NULL CONVENTION LOGIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
13894072
|
Filing Dt:
|
05/14/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
IMPLEMENTATION METHOD FOR FAST NCL DATA PATH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2017
|
Application #:
|
13964257
|
Filing Dt:
|
08/12/2013
|
|
Publication #:
|
|
Pub Dt:
|
03/13/2014
| | | | |
|
Title:
|
DYNAMICALLY RESIZABLE CIRCULAR BUFFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
13969675
|
Filing Dt:
|
08/19/2013
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
HUM GENERATION CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2017
|
Application #:
|
14099949
|
Filing Dt:
|
12/07/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
|
Title:
|
EXTENSIBLE ITERATIVE MULTIPLIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2018
|
Application #:
|
14136754
|
Filing Dt:
|
12/20/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/26/2014
| | | | |
|
Title:
|
SELECTIVELY COMBINABLE SHIFTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
14149009
|
Filing Dt:
|
01/07/2014
|
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
|
Title:
|
SOFTWARE BASED APPLICATION SPECIFIC INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
14153188
|
Filing Dt:
|
01/13/2014
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
SWITCH STATEMENT PREDICTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2017
|
Application #:
|
14153223
|
Filing Dt:
|
01/13/2014
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2014
| | | | |
|
Title:
|
CONTROL OF PRE-FETCH TRAFFIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2017
|
Application #:
|
14153240
|
Filing Dt:
|
01/13/2014
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
FILL PARTITIONING OF A SHARED CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
14157764
|
Filing Dt:
|
01/17/2014
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
|
Title:
|
ALLOCATING RESOURCES TO THREADS BASED ON SPECULATION METRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2016
|
Application #:
|
14157805
|
Filing Dt:
|
01/17/2014
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
|
Title:
|
REGISTER FILE HAVING A PLURALITY OF SUB-REGISTER FILES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2016
|
Application #:
|
14169601
|
Filing Dt:
|
01/31/2014
|
|
Publication #:
|
|
Pub Dt:
|
08/14/2014
| | | | |
|
Title:
|
SPECULATIVE LOAD ISSUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2017
|
Application #:
|
14169771
|
Filing Dt:
|
01/31/2014
|
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
|
Title:
|
INDIRECT BRANCH PREDICTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2018
|
Application #:
|
14169886
|
Filing Dt:
|
01/31/2014
|
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
|
Title:
|
MECHANISM FOR COPYING DATA IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
14189719
|
Filing Dt:
|
02/25/2014
|
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
|
Title:
|
MIGRATION OF DATA TO REGISTER FILE CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2017
|
Application #:
|
14271886
|
Filing Dt:
|
05/07/2014
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2015
| | | | |
|
Title:
|
SYSTEM FOR PROVIDING TRACE DATA IN A DATA PROCESSOR HAVING A PIPELINED ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2017
|
Application #:
|
14340932
|
Filing Dt:
|
07/25/2014
|
|
Publication #:
|
|
Pub Dt:
|
04/16/2015
| | | | |
|
Title:
|
PRIORITIZING INSTRUCTIONS BASED ON TYPE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2016
|
Application #:
|
14451279
|
Filing Dt:
|
08/04/2014
|
|
Publication #:
|
|
Pub Dt:
|
03/05/2015
| | | | |
|
Title:
|
CROSSING PIPELINED DATA BETWEEN CIRCUITRY IN DIFFERENT CLOCK DOMAINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2016
|
Application #:
|
14487678
|
Filing Dt:
|
09/16/2014
|
|
Publication #:
|
|
Pub Dt:
|
03/19/2015
| | | | |
|
Title:
|
MULTI-THRESHOLD CIRCUITRY BASED ON SILICON-ON-INSULATOR TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
14530624
|
Filing Dt:
|
10/31/2014
|
|
Publication #:
|
|
Pub Dt:
|
05/07/2015
| | | | |
|
Title:
|
LOGICAL ELEMENTS WITH SWITCHABLE CONNECTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2018
|
Application #:
|
14572186
|
Filing Dt:
|
12/16/2014
|
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
|
Title:
|
PROCESSOR WITH VIRTUALIZED INSTRUCTION SET ARCHITECTURE & METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2020
|
Application #:
|
14589693
|
Filing Dt:
|
01/05/2015
|
|
Title:
|
HARDWARE VIRTUALIZED INPUT OUTPUT MEMORY MANAGEMENT UNIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2017
|
Application #:
|
14596407
|
Filing Dt:
|
01/14/2015
|
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
|
Title:
|
STACK POINTER VALUE PREDICTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2018
|
Application #:
|
14598415
|
Filing Dt:
|
01/16/2015
|
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
|
Title:
|
Stack Saved Variable Pointer Value Prediction
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2016
|
Application #:
|
14608630
|
Filing Dt:
|
01/29/2015
|
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
|
Title:
|
Return Stack Buffer Having Multiple Address Slots Per Stack Entry
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2016
|
Application #:
|
14608745
|
Filing Dt:
|
01/29/2015
|
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
|
Title:
|
Storing Look-Up Table Indexes in a Return Stack Buffer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2017
|
Application #:
|
14612084
|
Filing Dt:
|
02/02/2015
|
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
|
Title:
|
PIPELINED ECC-PROTECTED MEMORY ACCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2020
|
Application #:
|
14612090
|
Filing Dt:
|
02/02/2015
|
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
|
Title:
|
MODELESS INSTRUCTION EXECUTION WITH 64/32-BIT ADDRESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2020
|
Application #:
|
14612104
|
Filing Dt:
|
02/02/2015
|
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
|
Title:
|
PROCESSOR SUPPORTING ARITHMETIC INSTRUCTIONS WITH BRANCH ON OVERFLOW & METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2017
|
Application #:
|
14625895
|
Filing Dt:
|
02/19/2015
|
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
|
Title:
|
Global Register Protection In A Multi-Threaded Processor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
14703483
|
Filing Dt:
|
05/04/2015
|
|
Publication #:
|
|
Pub Dt:
|
08/20/2015
| | | | |
|
Title:
|
MULTI-THRESHOLD FLASH NCL LOGIC CIRCUITRY WITH FLASH RESET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2017
|
Application #:
|
14715117
|
Filing Dt:
|
05/18/2015
|
|
Publication #:
|
|
Pub Dt:
|
11/24/2016
| | | | |
|
Title:
|
TRANSLATION LOOKASIDE BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
14722292
|
Filing Dt:
|
05/27/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/03/2015
| | | | |
|
Title:
|
Decoding Instructions That Are Modified By One Or More Other Instructions
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
14741738
|
Filing Dt:
|
06/17/2015
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2016
| | | | |
|
Title:
|
Fault Tolerant Processor for Real-Time Systems
|
|
