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Reel/Frame:023196/0907   Pages: 18
Recorded: 09/09/2009
Attorney Dkt #:68166426-001012
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 31
1
Patent #:
5901063
Issue Dt:
05/04/1999
Application #:
08804524
Filing Dt:
02/21/1997
Title:
A SYSTEM AND METHOD FOR EXTRACTING PARASITIC IMPEDANCE FROM AN INTEGRATED CIRCUIT LAYOUT
2
Patent #:
6057171
Issue Dt:
05/02/2000
Application #:
08937393
Filing Dt:
09/25/1997
Title:
METHODS FOR DETERMINING ON-CHIP INTERCONNECT PROCESS PARAMETERS
3
Patent #:
6291254
Issue Dt:
09/18/2001
Application #:
09244616
Filing Dt:
02/04/1999
Title:
METHODS FOR DETERMINING ON-CHIP INTERCONNECT PROCESS PARAMETERS
4
Patent #:
6312963
Issue Dt:
11/06/2001
Application #:
09245812
Filing Dt:
02/04/1999
Title:
METHODS FOR DETERMINING ON-CHIP INTERCONNECT PROCESS PARAMETERS
5
Patent #:
6381730
Issue Dt:
04/30/2002
Application #:
09350966
Filing Dt:
07/09/1999
Title:
METHOD AND SYSTEM FOR EXTRACTION OF PARASITIC INTERCONNECT IMPEDANCE INCLUDING INDUCTANCE
6
Patent #:
6403389
Issue Dt:
06/11/2002
Application #:
09373923
Filing Dt:
08/12/1999
Title:
METHOD FOR DETERMINING ON-CHIP SHEET RESISTIVITY
7
Patent #:
6493648
Issue Dt:
12/10/2002
Application #:
09375254
Filing Dt:
08/16/1999
Title:
METHOD AND APPARATUS FOR LOGIC SYNTHESIS (INFERRING COMPLEX COMPONENTS)
8
Patent #:
6574787
Issue Dt:
06/03/2003
Application #:
09375836
Filing Dt:
08/16/1999
Title:
METHOD AND APPARATUS FOR LOGIC SYNTHESIS (WORD ORIENTED NETLIST)
9
Patent #:
6519755
Issue Dt:
02/11/2003
Application #:
09375843
Filing Dt:
08/16/1999
Title:
METHOD AND APPARATUS FOR LOGIC SYNTHESIS WITH ELABORATION
10
Patent #:
6311312
Issue Dt:
10/30/2001
Application #:
09405510
Filing Dt:
09/23/1999
Title:
METHOD FOR MODELING A CONDUCTIVE SEMICONDUCTOR SUBSTRATE
11
Patent #:
6591407
Issue Dt:
07/08/2003
Application #:
09516489
Filing Dt:
03/01/2000
Title:
METHOD AND APPARATUS FOR INTERCONNECT-DRIVEN OPTIMIZATION OF INTEGRATED CIRCUIT DESIGN
12
Patent #:
6598209
Issue Dt:
07/22/2003
Application #:
09798016
Filing Dt:
02/28/2001
Title:
RTL POWER ANALYSIS USING GATE-LEVEL CELL POWER MODELS
13
Patent #:
6701505
Issue Dt:
03/02/2004
Application #:
10008458
Filing Dt:
11/30/2001
Title:
CIRCUIT OPTIMIZATION FOR MINIMUM PATH TIMING VIOLATIONS
14
Patent #:
6701506
Issue Dt:
03/02/2004
Application #:
10022743
Filing Dt:
12/14/2001
Title:
METHOD FOR MATCH DELAY BUFFER INSERTION
15
Patent #:
6754877
Issue Dt:
06/22/2004
Application #:
10022747
Filing Dt:
12/14/2001
Title:
METHOD FOR OPTIMAL DRIVER SELECTION
16
Patent #:
6701507
Issue Dt:
03/02/2004
Application #:
10022751
Filing Dt:
12/14/2001
Title:
METHOD FOR DETERMINING A ZERO-SKEW BUFFER INSERTION POINT
17
Patent #:
6698006
Issue Dt:
02/24/2004
Application #:
10023329
Filing Dt:
12/14/2001
Title:
METHOD FOR BALANCED-DELAY CLOCK TREE INSERTION
18
Patent #:
6643831
Issue Dt:
11/04/2003
Application #:
10057165
Filing Dt:
01/24/2002
Publication #:
US20020104063
Pub Dt:
08/01/2002
Title:
METHOD AND SYSTEM FOR EXTRACTION OF PARASITIC INTERCONNECT IMPEDANCE INCLUDING INDUCTANCE
19
Patent #:
6807660
Issue Dt:
10/19/2004
Application #:
10262914
Filing Dt:
10/01/2002
Title:
VECTORLESS INSTANTANEOUS CURRENT ESTIMATION
20
Patent #:
7222311
Issue Dt:
05/22/2007
Application #:
10387644
Filing Dt:
03/12/2003
Publication #:
US20030177455
Pub Dt:
09/18/2003
Title:
METHOD AND APPARATUS FOR INTERCONNECT-DRIVEN OPTIMIZATION OF INTEGRATED CIRCUIT DESIGN
21
Patent #:
6901565
Issue Dt:
05/31/2005
Application #:
10447076
Filing Dt:
05/27/2003
Publication #:
US20030208733
Pub Dt:
11/06/2003
Title:
RTL POWER ANALYSIS USING GATE-LEVEL CELL POWER MODELS
22
Patent #:
7222318
Issue Dt:
05/22/2007
Application #:
10627933
Filing Dt:
07/25/2003
Publication #:
US20040088664
Pub Dt:
05/06/2004
Title:
CIRCUIT OPTIMIZATION FOR MINIMUM PATH TIMING VIOLATIONS
23
Patent #:
7117457
Issue Dt:
10/03/2006
Application #:
10739659
Filing Dt:
12/17/2003
Publication #:
US20050138588
Pub Dt:
06/23/2005
Title:
CURRENT SCHEDULING SYSTEM AND METHOD FOR OPTIMIZING MULTI-THRESHOLD CMOS DESIGNS
24
Patent #:
7003741
Issue Dt:
02/21/2006
Application #:
10838811
Filing Dt:
05/03/2004
Publication #:
US20040210857
Pub Dt:
10/21/2004
Title:
METHOD FOR OPTIMAL DRIVER SELECTION
25
Patent #:
7185300
Issue Dt:
02/27/2007
Application #:
10926660
Filing Dt:
08/25/2004
Publication #:
US20050028119
Pub Dt:
02/03/2005
Title:
VECTORLESS INSTANTANEOUS CURRENT ESTIMATION
26
Patent #:
7590962
Issue Dt:
09/15/2009
Application #:
10998204
Filing Dt:
11/26/2004
Publication #:
US20090174434
Pub Dt:
07/09/2009
Title:
DESIGN METHOD AND ARCHITECTURE FOR POWER GATE SWITCH PLACEMENT
27
Patent #:
7774728
Issue Dt:
08/10/2010
Application #:
11150031
Filing Dt:
06/10/2005
Publication #:
US20060117282
Pub Dt:
06/01/2006
Title:
METHOD THAT ALLOWS FLEXIBLE EVALUATION OF POWER-GATED CIRCUITS
28
Patent #:
7323909
Issue Dt:
01/29/2008
Application #:
11193149
Filing Dt:
07/29/2005
Publication #:
US20070024318
Pub Dt:
02/01/2007
Title:
AUTOMATIC EXTENSION OF CLOCK GATING TECHNIQUE TO FINE-GRAINED POWER GATING
29
Patent #:
7509613
Issue Dt:
03/24/2009
Application #:
11331913
Filing Dt:
01/13/2006
Publication #:
US20070168899
Pub Dt:
07/19/2007
Title:
DESIGN METHOD AND ARCHITECTURE FOR POWER GATE SWITCH PLACEMENT AND INTERCONNECTION USING TAPLESS LIBRARIES
30
Patent #:
7752578
Issue Dt:
07/06/2010
Application #:
11551149
Filing Dt:
10/19/2006
Publication #:
US20080098335
Pub Dt:
04/24/2008
Title:
AUTOMATIC VOLTAGE DROP OPTIMIZATION
31
Patent #:
7750680
Issue Dt:
07/06/2010
Application #:
11952937
Filing Dt:
12/07/2007
Publication #:
US20080088344
Pub Dt:
04/17/2008
Title:
AUTOMATIC EXTENSION OF CLOCK GATING TECHNIQUE TO FINE-GRAINED POWER GATING
Assignor
1
FOCUS VENTURES II, LP
Exec Dt:
09/04/2009
Assignee
1
SEQUENCE DESIGN, INC.
440 NORTH WOLFE ROAD
SUNNYVALE, CALIFORNIA 94085
Correspondence name and address
BAKER & MCKENZIE LLP
2001 ROSS AVENUE, SUITE 2300
DALLAS, TX 75201

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