Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 021794/0912 | |
| Pages: | 4 |
| | Recorded: | 11/07/2008 | | |
| Attorney Dkt #: | 705328.1 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
10
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Patent #:
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Issue Dt:
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06/30/1998
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Application #:
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08725685
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Filing Dt:
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10/02/1996
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Title:
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ADDRESS GENERATOR FOR ERROR CONTROL SYSTEM
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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08842441
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Filing Dt:
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04/24/1997
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Title:
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ADAPTABLE OUTPUT PHASE DELAY COMPENSATION CIRCUIT AND METHOD THEREOF
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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08932384
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Filing Dt:
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09/17/1997
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Title:
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MAIN AMPLIFIER WITH FAST OUTPUT DISABLEMENT
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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08997509
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Filing Dt:
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12/23/1997
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Title:
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DRIVING MEMORY BITLINES USING BOOSTED VOLTAGE
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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08997541
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Filing Dt:
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12/23/1997
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Title:
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VOLTAGE PUMP FOR INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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09064190
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Filing Dt:
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04/22/1998
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Title:
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OFFSET-COMPENSATED PEAK DETECTOR WITH OUTPUT BUFFERING
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09111277
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Filing Dt:
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07/07/1998
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Title:
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SYSTEM AND METHOD FOR COLUMN ACCESS IN RANDOM ACCESS MEMORIES
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09227574
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Filing Dt:
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01/08/1999
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Title:
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PROGRAMMABLE DYNAMIC RANGE SIGMA DELTA A/D CONVERTER
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09250161
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Filing Dt:
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02/16/1999
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Title:
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SELF-ADJUSTING CLOCK PHASE CONTROLLED ARCHITECTURE
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09291328
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Filing Dt:
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04/15/1999
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Title:
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REDUCING BIAS CURRENT SETTLING TIME IN MAGNETO-RESISTIVE HEAD PRE-AMPLIFIERS
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Assignee
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| 5665 PLAZA DRIVE |
| CYPRESS, CALIFORNIA 90630 |
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Correspondence name and address
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MITSUBISHI ELECTRIC & ELECTRONICS USA
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5665 PLAZA DRIVE
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CYPRESS, CA 90630
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