Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 014292/0914 | |
| Pages: | 4 |
| | Recorded: | 01/30/2004 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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10243544
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Filing Dt:
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09/12/2002
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Publication #:
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Pub Dt:
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03/18/2004
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Title:
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SYSTEM AND METHOD FOR TESTING ONE OR MORE DIES ON A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10431996
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Filing Dt:
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05/07/2003
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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MULTI-THREADED EMBEDDED PROCESSOR USING DETERMINISTIC INSTRUCTION MEMORY TO GUARANTEE EXECUTION OF PRE-SELECTED THREADS DURING BLOCKING EVENTS
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Patent #:
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Issue Dt:
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04/19/2005
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Application #:
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10447018
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Filing Dt:
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05/28/2003
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Publication #:
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Pub Dt:
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12/02/2004
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Title:
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METHODS AND APPARATUS FOR PROVIDING AN ANTIFUSE FUNCTION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10609248
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Filing Dt:
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06/26/2003
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Publication #:
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Pub Dt:
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12/30/2004
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Title:
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Current source
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Assignee
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| ST. MARTIN-STR. 53 |
| 81669 MUNICH, GERMANY |
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Correspondence name and address
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INFINEON TECHNOLOGIES NORTH AMERICA CORP
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C/O SIEMENS CORPORATION, ERIK O. BERGER
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170 WOOD AVENUE SOUTH
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INTELLECTUAL PROPERTY DEPARTMENT
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ISELIN, NJ 08830
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