Patent Assignment Details
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| Reel/Frame: | 035909/0919 | |
| Pages: | 7 |
| | Recorded: | 06/15/2015 | | |
| Attorney Dkt #: | 13335/15042 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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10/18/2016
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Application #:
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14738765
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Filing Dt:
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06/12/2015
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Title:
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METHOD FOR USING SEQUENTIAL DECOMPRESSION LOGIC FOR VLSI TEST IN A PHYSICALLY EFFICIENT CONSTRUCTION
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Assignee
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| 2655 SEELY AVENUE |
| BUILDING 5 |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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CADENCE DESIGN SYSTEMS, INC. - KENYON
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1801 PAGE MILL ROAD
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SUITE 210
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PALO ALTO, CA 94304-1216
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