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Reel/Frame:064908/0920   Pages: 13
Recorded: 09/05/2023
Attorney Dkt #:392739-00007
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED ON REEL 038378 FRAME 0418. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME.
Total properties: 80
1
Patent #:
9252172
Issue Dt:
02/02/2016
Application #:
13149628
Filing Dt:
05/31/2011
Publication #:
US20120306038
Pub Dt:
12/06/2012
Title:
Semiconductor Device and Method of Forming EWLB Semiconductor Package with Vertical Interconnect Structure and Cavity Region
2
Patent #:
9190340
Issue Dt:
11/17/2015
Application #:
13163026
Filing Dt:
06/17/2011
Publication #:
US20120319302
Pub Dt:
12/20/2012
Title:
Semiconductor Device and Method of Forming RF FEM and RF Transceiver in Semiconductor Package
3
Patent #:
8435881
Issue Dt:
05/07/2013
Application #:
13167566
Filing Dt:
06/23/2011
Publication #:
US20120326297
Pub Dt:
12/27/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
4
Patent #:
9324659
Issue Dt:
04/26/2016
Application #:
13195636
Filing Dt:
08/01/2011
Publication #:
US20130032952
Pub Dt:
02/07/2013
Title:
Semiconductor Device and Method of Forming POP With Stacked Semiconductor Die and Bumps Formed Directly on the Lower Die
5
Patent #:
9190297
Issue Dt:
11/17/2015
Application #:
13208027
Filing Dt:
08/11/2011
Publication #:
US20130037936
Pub Dt:
02/14/2013
Title:
Semiconductor Device and Method of Forming a Stackable Semiconductor Package with Vertically-Oriented Discrete Electrical Devices as Interconnect Structures
6
Patent #:
NONE
Issue Dt:
Application #:
13218388
Filing Dt:
08/25/2011
Publication #:
US20130049188
Pub Dt:
02/28/2013
Title:
Semiconductor Device and Method of Forming TIM Within Recesses of MUF Material
7
Patent #:
10388584
Issue Dt:
08/20/2019
Application #:
13225683
Filing Dt:
09/06/2011
Publication #:
US20130056867
Pub Dt:
03/07/2013
Title:
Semiconductor device and method of forming FO-WLCSP with recessed interconnect area in peripheral region of semiconductor die
8
Patent #:
10163744
Issue Dt:
12/25/2018
Application #:
13226767
Filing Dt:
09/07/2011
Publication #:
US20130056862
Pub Dt:
03/07/2013
Title:
Semiconductor Device and Method of Forming a Low Profile Dual-Purpose Shield and Heat-Dissipation Structure
9
Patent #:
9230933
Issue Dt:
01/05/2016
Application #:
13234366
Filing Dt:
09/16/2011
Publication #:
US20130069221
Pub Dt:
03/21/2013
Title:
Semiconductor Device and Method of Forming Conductive Protrusions Over Conductive Pillars or Bond Pads as Fixed Offset Vertical Interconnect Structure
10
Patent #:
9177832
Issue Dt:
11/03/2015
Application #:
13234535
Filing Dt:
09/16/2011
Publication #:
US20130069222
Pub Dt:
03/21/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A RECONFIGURED STACKABLE WAFER LEVEL PACKAGE WITH VERTICAL INTERCONNECT
11
Patent #:
9275877
Issue Dt:
03/01/2016
Application #:
13236952
Filing Dt:
09/20/2011
Publication #:
US20130069241
Pub Dt:
03/21/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR PACKAGE USING PANEL FORM CARRIER
12
Patent #:
9484259
Issue Dt:
11/01/2016
Application #:
13239080
Filing Dt:
09/21/2011
Publication #:
US20130069225
Pub Dt:
03/21/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE
13
Patent #:
8815650
Issue Dt:
08/26/2014
Application #:
13242656
Filing Dt:
09/23/2011
Publication #:
US20130214430
Pub Dt:
08/22/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METHOD OF MANUFACTURE THEREOF
14
Patent #:
9679863
Issue Dt:
06/13/2017
Application #:
13243214
Filing Dt:
09/23/2011
Publication #:
US20130075936
Pub Dt:
03/28/2013
Title:
Semiconductor Device and Method of Forming Interconnect Substrate for FO-WLCSP
15
Patent #:
9385009
Issue Dt:
07/05/2016
Application #:
13243558
Filing Dt:
09/23/2011
Publication #:
US20130075924
Pub Dt:
03/28/2013
Title:
Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP
16
Patent #:
9054100
Issue Dt:
06/09/2015
Application #:
13287006
Filing Dt:
11/01/2011
Publication #:
US20130105967
Pub Dt:
05/02/2013
Title:
SEMICONDUCTOR DIE AND METHOD OF FORMING SLOPED SURFACE IN PHOTORESIST LAYER TO ENHANCE FLOW OF UNDERFILL MATERIAL BETWEEN SEMICONDUCTOR DIE AND SUBSTRATE
17
Patent #:
9281228
Issue Dt:
03/08/2016
Application #:
13287035
Filing Dt:
11/01/2011
Publication #:
US20130105963
Pub Dt:
05/02/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THERMAL INTERFACE MATERIAL AND HEAT SPREADER OVER SEMICONDUCTOR DIE
18
Patent #:
NONE
Issue Dt:
Application #:
13289811
Filing Dt:
11/04/2011
Publication #:
US20130113118
Pub Dt:
05/09/2013
Title:
Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning Layer
19
Patent #:
8952529
Issue Dt:
02/10/2015
Application #:
13303019
Filing Dt:
11/22/2011
Publication #:
US20130127042
Pub Dt:
05/23/2013
Title:
SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYER OVER SUBSTRATE WITH VENTS TO CHANNEL BUMP MATERIAL AND REDUCE INTERCONNECT VOIDS
20
Patent #:
9142522
Issue Dt:
09/22/2015
Application #:
13307849
Filing Dt:
11/30/2011
Publication #:
US20130134580
Pub Dt:
05/30/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RDL UNDER BUMP FOR ELECTRICAL CONNECTION TO ENCLOSED BUMP
21
Patent #:
8963326
Issue Dt:
02/24/2015
Application #:
13312730
Filing Dt:
12/06/2011
Publication #:
US20130140691
Pub Dt:
06/06/2013
Title:
Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration
22
Patent #:
8502391
Issue Dt:
08/06/2013
Application #:
13314984
Filing Dt:
12/08/2011
Publication #:
US20130147053
Pub Dt:
06/13/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF MAKING SINGLE LAYER SUBSTRATE WITH ASYMMETRICAL FIBERS AND REDUCED WARPAGE
23
Patent #:
8610286
Issue Dt:
12/17/2013
Application #:
13315010
Filing Dt:
12/08/2011
Publication #:
US20130147054
Pub Dt:
06/13/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THICK ENCAPSULANT FOR STIFFNESS WITH RECESSES FOR STRESS RELIEF IN FO-WLCSP
24
Patent #:
8558389
Issue Dt:
10/15/2013
Application #:
13315033
Filing Dt:
12/08/2011
Publication #:
US20130147055
Pub Dt:
06/13/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING GUARD RING AROUND CONDUCTIVE TSV THROUGH SEMICONDUCTOR WAFER
25
Patent #:
8741764
Issue Dt:
06/03/2014
Application #:
13324349
Filing Dt:
12/13/2011
Publication #:
US20130146872
Pub Dt:
06/13/2013
Title:
Semiconductor Device and Method of Forming Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate
26
Patent #:
9685402
Issue Dt:
06/20/2017
Application #:
13324397
Filing Dt:
12/13/2011
Publication #:
US20130147035
Pub Dt:
06/13/2013
Title:
Semiconductor Device and Method of Forming Recesses in Conductive Layer to Detect Continuity for Interconnect Between Semiconductor Die and Substrate
27
Patent #:
8809191
Issue Dt:
08/19/2014
Application #:
13324446
Filing Dt:
12/13/2011
Publication #:
US20130147036
Pub Dt:
06/13/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM STRUCTURE ON BACK SURFACE OF TSV SEMICONDUCTOR WAFER
28
Patent #:
8592992
Issue Dt:
11/26/2013
Application #:
13326128
Filing Dt:
12/14/2011
Publication #:
US20130154108
Pub Dt:
06/20/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE WITH CONDUCTIVE MICRO VIA ARRAY FOR 3-D FO-WLCSP
29
Patent #:
8742591
Issue Dt:
06/03/2014
Application #:
13333395
Filing Dt:
12/21/2011
Publication #:
US20130161824
Pub Dt:
06/27/2013
Title:
Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief
30
Patent #:
9484319
Issue Dt:
11/01/2016
Application #:
13336860
Filing Dt:
12/23/2011
Publication #:
US20130161833
Pub Dt:
06/27/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING EXTENDED SEMICONDUCTOR DEVICE WITH FAN-OUT INTERCONNECT STRUCTURE TO REDUCE COMPLEXITY OF SUBSTRATE
31
Patent #:
8524577
Issue Dt:
09/03/2013
Application #:
13366008
Filing Dt:
02/03/2012
Publication #:
US20130127018
Pub Dt:
05/23/2013
Title:
Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure
32
Patent #:
8642384
Issue Dt:
02/04/2014
Application #:
13417034
Filing Dt:
03/09/2012
Publication #:
US20130234318
Pub Dt:
09/12/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NON-LINEAR INTERCONNECT LAYER WITH EXTENDED LENGTH FOR JOINT RELIABILITY
33
Patent #:
9824923
Issue Dt:
11/21/2017
Application #:
13468981
Filing Dt:
05/10/2012
Publication #:
US20130093100
Pub Dt:
04/18/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLAR HAVING AN EXPANDED BASE
34
Patent #:
9082832
Issue Dt:
07/14/2015
Application #:
13478008
Filing Dt:
05/22/2012
Publication #:
US20130069227
Pub Dt:
03/21/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE
35
Patent #:
9564413
Issue Dt:
02/07/2017
Application #:
13545887
Filing Dt:
07/10/2012
Publication #:
US20130069252
Pub Dt:
03/21/2013
Title:
Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus
36
Patent #:
9252032
Issue Dt:
02/02/2016
Application #:
13566872
Filing Dt:
08/03/2012
Publication #:
US20120299174
Pub Dt:
11/29/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF STACKING SEMICONDUCTOR DIE IN MOLD LASER PACKAGE INTERCONNECTED BY BUMPS AND CONDUCTIVE VIAS
37
Patent #:
8519544
Issue Dt:
08/27/2013
Application #:
13570979
Filing Dt:
08/09/2012
Publication #:
US20120306097
Pub Dt:
12/06/2012
Title:
Semiconductor Device and Method of Forming WLCSP Structure using Protruded MLP
38
Patent #:
9082638
Issue Dt:
07/14/2015
Application #:
13572517
Filing Dt:
08/10/2012
Publication #:
US20120299149
Pub Dt:
11/29/2012
Title:
Semicinductor Device with Cross-Talk Isolation Using M-CAP
39
Patent #:
9252075
Issue Dt:
02/02/2016
Application #:
13604539
Filing Dt:
09/05/2012
Publication #:
US20120326329
Pub Dt:
12/27/2012
Title:
Semiconductor Device and Method of Forming a Conductive Via-in-Via Structure
40
Patent #:
9263301
Issue Dt:
02/16/2016
Application #:
13607204
Filing Dt:
09/07/2012
Publication #:
US20130001771
Pub Dt:
01/03/2013
Title:
Semiconductor Device and Method of Forming FO-WLCSP with Discrete Semiconductor Components Mounted Under and Over Semiconductor Die
41
Patent #:
NONE
Issue Dt:
Application #:
13609003
Filing Dt:
09/10/2012
Publication #:
US20130001773
Pub Dt:
01/03/2013
Title:
Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump
42
Patent #:
NONE
Issue Dt:
Application #:
13609050
Filing Dt:
09/10/2012
Publication #:
US20130001762
Pub Dt:
01/03/2013
Title:
Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die
43
Patent #:
9240384
Issue Dt:
01/19/2016
Application #:
13621804
Filing Dt:
09/17/2012
Publication #:
US20130015575
Pub Dt:
01/17/2013
Title:
SEMICONDUCTOR DEVICE WITH SOLDER BUMP FORMED ON HIGH TOPOGRAPHY PLATED CU PADS
44
Patent #:
9177930
Issue Dt:
11/03/2015
Application #:
13621810
Filing Dt:
09/17/2012
Publication #:
US20130015576
Pub Dt:
01/17/2013
Title:
SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
45
Patent #:
9337141
Issue Dt:
05/10/2016
Application #:
13622280
Filing Dt:
09/18/2012
Publication #:
US20130015555
Pub Dt:
01/17/2013
Title:
Method of Forming an Inductor on a Semiconductor Wafer
46
Patent #:
9142431
Issue Dt:
09/22/2015
Application #:
13622297
Filing Dt:
09/18/2012
Publication #:
US20130015577
Pub Dt:
01/17/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH CAVITIES FORMED THROUGH ETCH-RESISTANT CONDUCTIVE LAYER FOR BUMP LOCKING
47
Patent #:
9842808
Issue Dt:
12/12/2017
Application #:
13645385
Filing Dt:
10/04/2012
Publication #:
US20130026654
Pub Dt:
01/31/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT IN FO-WLCSP USING LEADFRAME DISPOSED BETWEEN SEMICONDUCTOR DIE
48
Patent #:
9159665
Issue Dt:
10/13/2015
Application #:
13645397
Filing Dt:
10/04/2012
Publication #:
US20130026628
Pub Dt:
01/31/2013
Title:
FLIP CHIP INTERCONNECTION HAVING NARROW INTERCONNECTION SITES ON THE SUBSTRATE
49
Patent #:
9704857
Issue Dt:
07/11/2017
Application #:
13678134
Filing Dt:
11/15/2012
Publication #:
US20130069197
Pub Dt:
03/21/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RF FEM WITH LC FILTER AND IPD FILTER OVER SUBSTRATE
50
Patent #:
9515016
Issue Dt:
12/06/2016
Application #:
13682281
Filing Dt:
11/20/2012
Publication #:
US20130075899
Pub Dt:
03/28/2013
Title:
SEMICONDUCTOR PACKAGE AND METHOD OF FORMING Z-DIRECTION CONDUCTIVE POSTS EMBEDDED IN STRUCTURALLY PROTECTIVE ENCAPSULANT
51
Patent #:
9418913
Issue Dt:
08/16/2016
Application #:
13682510
Filing Dt:
11/20/2012
Publication #:
US20130075900
Pub Dt:
03/28/2013
Title:
Semiconductor Device and Method of Forming Insulating Layer on Conductive Traces for Electrical Isolation in Fine Pitch Bonding
52
Patent #:
9099455
Issue Dt:
08/04/2015
Application #:
13683884
Filing Dt:
11/21/2012
Publication #:
US20130075902
Pub Dt:
03/28/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS EMBEDDED IN PHOTOSENSITIVE ENCAPSULANT
53
Patent #:
9064859
Issue Dt:
06/23/2015
Application #:
13683946
Filing Dt:
11/21/2012
Publication #:
US20130105970
Pub Dt:
05/02/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS AND HEAT SINK OVER SEMICONDUCTOR DIE USING LEADFRAME
54
Patent #:
9153476
Issue Dt:
10/06/2015
Application #:
13691464
Filing Dt:
11/30/2012
Publication #:
US20130087898
Pub Dt:
04/11/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED MULTI-DIE LEADFRAME FOR ELECTRICAL INTERCONNECT OF STACKED SEMICONDUCTOR DIE
55
Patent #:
9240380
Issue Dt:
01/19/2016
Application #:
13715424
Filing Dt:
12/14/2012
Publication #:
US20140327145
Pub Dt:
11/06/2014
Title:
Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect
56
Patent #:
9484334
Issue Dt:
11/01/2016
Application #:
13716799
Filing Dt:
12/17/2012
Publication #:
US20130099356
Pub Dt:
04/25/2013
Title:
Semiconductor Device and Method of Forming Directional RF Coupler with IPD for Additional RF Signal Processing
57
Patent #:
9460972
Issue Dt:
10/04/2016
Application #:
13720516
Filing Dt:
12/19/2012
Publication #:
US20130175701
Pub Dt:
07/11/2013
Title:
Semiconductor Device and Method of Forming Reduced Surface Roughness in Molded Underfill for Improved C-SAM Inspection
58
Patent #:
10068843
Issue Dt:
09/04/2018
Application #:
13726467
Filing Dt:
12/24/2012
Publication #:
US20130140683
Pub Dt:
06/06/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY IN BUILD-UP INTERCONNECT STRUCTURE FOR SHORT SIGNAL PATH BETWEEN DIE
59
Patent #:
8742566
Issue Dt:
06/03/2014
Application #:
13727116
Filing Dt:
12/26/2012
Publication #:
US20130134586
Pub Dt:
05/30/2013
Title:
SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
60
Patent #:
9520365
Issue Dt:
12/13/2016
Application #:
13728012
Filing Dt:
12/27/2012
Publication #:
US20130140719
Pub Dt:
06/06/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS
61
Patent #:
8921161
Issue Dt:
12/30/2014
Application #:
13732150
Filing Dt:
12/31/2012
Publication #:
US20130119559
Pub Dt:
05/16/2013
Title:
Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die
62
Patent #:
9030030
Issue Dt:
05/12/2015
Application #:
13760187
Filing Dt:
02/06/2013
Publication #:
US20130147065
Pub Dt:
06/13/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL
63
Patent #:
8703548
Issue Dt:
04/22/2014
Application #:
13765478
Filing Dt:
02/12/2013
Publication #:
US20130171800
Pub Dt:
07/04/2013
Title:
Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
64
Patent #:
9236332
Issue Dt:
01/12/2016
Application #:
13765594
Filing Dt:
02/12/2013
Publication #:
US20130154067
Pub Dt:
06/20/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECT STRUCTURE ON LEADFRAME
65
Patent #:
8878359
Issue Dt:
11/04/2014
Application #:
13766493
Filing Dt:
02/13/2013
Publication #:
US20130147019
Pub Dt:
06/13/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
66
Patent #:
8866275
Issue Dt:
10/21/2014
Application #:
13766646
Filing Dt:
02/13/2013
Publication #:
US20130154076
Pub Dt:
06/20/2013
Title:
LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT
67
Patent #:
8709935
Issue Dt:
04/29/2014
Application #:
13768862
Filing Dt:
02/15/2013
Publication #:
US20130154090
Pub Dt:
06/20/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
68
Patent #:
8836097
Issue Dt:
09/16/2014
Application #:
13769302
Filing Dt:
02/16/2013
Publication #:
US20130200527
Pub Dt:
08/08/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOLDING
69
Patent #:
9881894
Issue Dt:
01/30/2018
Application #:
13771825
Filing Dt:
02/20/2013
Publication #:
US20130234322
Pub Dt:
09/12/2013
Title:
Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application Processor and Memory Integration
70
Patent #:
9293401
Issue Dt:
03/22/2016
Application #:
13772683
Filing Dt:
02/21/2013
Publication #:
US20130228917
Pub Dt:
09/05/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING A LOW PROFILE EMBEDDED WAFER LEVEL BALL GRID ARRAY MOLDED LASER PACKAGE (EWLB-MLP)
71
Patent #:
8759155
Issue Dt:
06/24/2014
Application #:
13782618
Filing Dt:
03/01/2013
Publication #:
US20130175696
Pub Dt:
07/11/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
72
Patent #:
9449925
Issue Dt:
09/20/2016
Application #:
13782939
Filing Dt:
03/01/2013
Publication #:
US20130175668
Pub Dt:
07/11/2013
Title:
Integrated Passive Devices
73
Patent #:
9064936
Issue Dt:
06/23/2015
Application #:
13832333
Filing Dt:
03/15/2013
Publication #:
US20130200528
Pub Dt:
08/08/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
74
Patent #:
8790962
Issue Dt:
07/29/2014
Application #:
13845329
Filing Dt:
03/18/2013
Publication #:
US20130207247
Pub Dt:
08/15/2013
Title:
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure
75
Patent #:
9524938
Issue Dt:
12/20/2016
Application #:
13845409
Filing Dt:
03/18/2013
Publication #:
US20130214385
Pub Dt:
08/22/2013
Title:
PACKAGE-IN-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS
76
Patent #:
9679824
Issue Dt:
06/13/2017
Application #:
13845542
Filing Dt:
03/18/2013
Publication #:
US20130214409
Pub Dt:
08/22/2013
Title:
Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP
77
Patent #:
9589910
Issue Dt:
03/07/2017
Application #:
13846014
Filing Dt:
03/18/2013
Publication #:
US20130214398
Pub Dt:
08/22/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE LEADS FROM BASE SUBSTRATE AS STANDOFF FOR STACKING SEMICONDUCTOR DIE
78
Patent #:
8912650
Issue Dt:
12/16/2014
Application #:
13846742
Filing Dt:
03/18/2013
Publication #:
US20130228919
Pub Dt:
09/05/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
79
Patent #:
9553162
Issue Dt:
01/24/2017
Application #:
13853969
Filing Dt:
03/29/2013
Publication #:
US20130221452
Pub Dt:
08/29/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DIE WITH ACTIVE REGION RESPONSIVE TO EXTERNAL STIMULUS
80
Patent #:
8896133
Issue Dt:
11/25/2014
Application #:
13870928
Filing Dt:
04/25/2013
Publication #:
US20130234324
Pub Dt:
09/12/2013
Title:
Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate
Assignor
1
STATS CHIPPAC LTD.
Exec Dt:
03/29/2016
Assignee
1
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23
SINGAPORE, SINGAPORE
Correspondence name and address
KATTEN MUCHIN ROSENMAN LLP
1919 PENNSYLVANIA AVE., NW - SUITE 800
WASHINGTON, DC 20006

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