Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 018228/0921 | |
| Pages: | 3 |
| | Recorded: | 08/23/2006 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
|
11508585
|
Filing Dt:
|
08/23/2006
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
|
Title:
|
CIRCUITS AND ASSOCIATED METHODS FOR IMPROVED DEBUG AND TEST OF AN APPLICATION INTEGRATED CIRCUIT
|
|
|
Assignee
|
|
|
|
|
| 1621 BABER LANE |
| IP LEGAL DEPT., MAIL STOP D-106 |
| MILPITAS, CALIFORNIA 95035 |
|
|
Correspondence name and address
|
| |
LSI LOGIC CORPORATION
|
| |
INTELLECTUAL PROPERTY LEGAL DEPARTMENT
|
| |
1621 BARBER LANE
|
| |
MAIL STOP D-106
|
| |
MILPITAS, CA 95035
|
Search Results as of:
05/24/2024 09:57 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
