USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	045168/0922			Pages:	4
		Recorded:	01/26/2018
Attorney Dkt #:	075803.000002
Conveyance:	CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).

Total properties: 73

Patent #:	7269713	Issue Dt:	09/11/2007	Application #:	10468434	Filing Dt:	09/21/2004
Publication #:	US20050021931	Pub Dt:	01/27/2005
Title:	ADJUSTING THREAD INSTRUCTION ISSUE RATE BASED ON DEVIATION OF ACTUAL EXECUTED NUMBER FROM INTENDED RATE CUMULATIVE NUMBER

Patent #:	7712101	Issue Dt:	05/04/2010	Application #:	10949958	Filing Dt:	09/24/2004
Publication #:	US20050235126	Pub Dt:	10/20/2005
Title:	METHOD AND APPARATUS FOR DYNAMIC ALLOCATION OF RESOURCES TO EXECUTING THREADS IN A MULTI-THREADED PROCESSOR

Patent #:	7337303	Issue Dt:	02/26/2008	Application #:	11524822	Filing Dt:	09/21/2006
Publication #:	US20070016757	Pub Dt:	01/18/2007
Title:	THREAD INSTRUCTION ISSUE POOL COUNTER DECREMENTED UPON EXECUTION AND INCREMENTED AT DESIRED ISSUE RATE

Patent #:	7594097	Issue Dt:	09/22/2009	Application #:	11632567	Filing Dt:	01/11/2008
Publication #:	US20080250234	Pub Dt:	10/09/2008
Title:	MICROPROCESSOR OUTPUT PORTS AND CONTROL OF INSTRUCTIONS PROVIDED THEREFROM

Patent #:	10437598	Issue Dt:	10/08/2019	Application #:	11704725	Filing Dt:	02/09/2007
Publication #:	US20070204134	Pub Dt:	08/30/2007
Title:	METHOD AND APPARATUS FOR SELECTING AMONG A PLURALITY OF INSTRUCTION SETS TO A MICROPROCESSOR

Patent #:	8209520	Issue Dt:	06/26/2012	Application #:	11725631	Filing Dt:	03/20/2007
Publication #:	US20070288723	Pub Dt:	12/13/2007
Title:	EXPANDED FUNCTIONALITY OF PROCESSOR OPERATIONS WITHIN A FIXED WIDTH INSTRUCTION ENCODING

Patent #:	9348600	Issue Dt:	05/24/2016	Application #:	12322942	Filing Dt:	02/09/2009
Publication #:	US20090210660	Pub Dt:	08/20/2009
Title:	Prioritising of instruction fetching in microprocessor systems

Patent #:	8560813	Issue Dt:	10/15/2013	Application #:	12383118	Filing Dt:	03/19/2009
Publication #:	US20090249037	Pub Dt:	10/01/2009
Title:	Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision

Patent #:	8775875	Issue Dt:	07/08/2014	Application #:	12387152	Filing Dt:	04/28/2009
Publication #:	US20090287907	Pub Dt:	11/19/2009
Title:	SYSTEM FOR PROVIDING TRACE DATA IN A DATA PROCESSOR HAVING A PIPELINED ARCHITECTURE

Patent #:	9189241	Issue Dt:	11/17/2015	Application #:	12584759	Filing Dt:	09/11/2009
Publication #:	US20100275211	Pub Dt:	10/28/2010
Title:	Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor

Patent #:	8234455	Issue Dt:	07/31/2012	Application #:	12586649	Filing Dt:	09/25/2009
Publication #:	US20100257322	Pub Dt:	10/07/2010
Title:	METHOD AND APPARATUS FOR ENSURING DATA CACHE COHERENCY

Patent #:	9612844	Issue Dt:	04/04/2017	Application #:	13138176	Filing Dt:	09/20/2011
Publication #:	US20120124338	Pub Dt:	05/17/2012
Title:	SCHEDULING EXECUTION OF INSTRUCTIONS ON A PROCESSOR HAVING MULTIPLE HARDWARE THREADS WITH DIFFERENT EXECUTION RESOURCES

Patent #:	9075724	Issue Dt:	07/07/2015	Application #:	13555894	Filing Dt:	07/23/2012
Publication #:	US20130219145	Pub Dt:	08/22/2013
Title:	METHOD AND APPARATUS FOR ENSURING DATA CACHE COHERENCY

Patent #:	NONE	Issue Dt:		Application #:	13751145	Filing Dt:	01/28/2013
Publication #:	US20140047218	Pub Dt:	02/13/2014
Title:	MULTI-STAGE REGISTER RENAMING USING DEPENDENCY REMOVAL

Patent #:	8996847	Issue Dt:	03/31/2015	Application #:	13780115	Filing Dt:	02/28/2013
Publication #:	US20140068232	Pub Dt:	03/06/2014
Title:	GLOBAL REGISTER PROTECTION IN A MULTI-THREADED PROCESSOR

Patent #:	9824003	Issue Dt:	11/21/2017	Application #:	13964257	Filing Dt:	08/12/2013
Publication #:	US20140075144	Pub Dt:	03/13/2014
Title:	DYNAMICALLY RESIZABLE CIRCULAR BUFFERS

Patent #:	9298467	Issue Dt:	03/29/2016	Application #:	14153188	Filing Dt:	01/13/2014
Publication #:	US20140201509	Pub Dt:	07/17/2014
Title:	SWITCH STATEMENT PREDICTION

Patent #:	9658962	Issue Dt:	05/23/2017	Application #:	14153223	Filing Dt:	01/13/2014
Publication #:	US20140325159	Pub Dt:	10/30/2014
Title:	CONTROL OF PRE-FETCH TRAFFIC

Patent #:	9645945	Issue Dt:	05/09/2017	Application #:	14153240	Filing Dt:	01/13/2014
Publication #:	US20140201452	Pub Dt:	07/17/2014
Title:	FILL PARTITIONING OF A SHARED CACHE

Patent #:	9086721	Issue Dt:	07/21/2015	Application #:	14157764	Filing Dt:	01/17/2014
Publication #:	US20140218224	Pub Dt:	08/07/2014
Title:	ALLOCATING RESOURCES TO THREADS BASED ON SPECULATION METRIC

Patent #:	9304934	Issue Dt:	04/05/2016	Application #:	14157805	Filing Dt:	01/17/2014
Publication #:	US20140223101	Pub Dt:	08/07/2014
Title:	REGISTER FILE HAVING A PLURALITY OF SUB-REGISTER FILES

Patent #:	9792123	Issue Dt:	10/17/2017	Application #:	14169771	Filing Dt:	01/31/2014
Publication #:	US20140281441	Pub Dt:	09/18/2014
Title:	INDIRECT BRANCH PREDICTION

Patent #:	9292450	Issue Dt:	03/22/2016	Application #:	14189719	Filing Dt:	02/25/2014
Publication #:	US20140258627	Pub Dt:	09/11/2014
Title:	MIGRATION OF DATA TO REGISTER FILE CACHE

Patent #:	9720695	Issue Dt:	08/01/2017	Application #:	14271886	Filing Dt:	05/07/2014
Publication #:	US20150012728	Pub Dt:	01/08/2015
Title:	SYSTEM FOR PROVIDING TRACE DATA IN A DATA PROCESSOR HAVING A PIPELINED ARCHITECTURE

Patent #:	9558001	Issue Dt:	01/31/2017	Application #:	14340932	Filing Dt:	07/25/2014
Publication #:	US20150106595	Pub Dt:	04/16/2015
Title:	PRIORITIZING INSTRUCTIONS BASED ON TYPE

Patent #:	9367286	Issue Dt:	06/14/2016	Application #:	14451279	Filing Dt:	08/04/2014
Publication #:	US20150067384	Pub Dt:	03/05/2015
Title:	CROSSING PIPELINED DATA BETWEEN CIRCUITRY IN DIFFERENT CLOCK DOMAINS

Patent #:	NONE	Issue Dt:		Application #:	14456873	Filing Dt:	08/11/2014
Publication #:	US20150058574	Pub Dt:	02/26/2015
Title:	Increasing The Efficiency of Memory Resources In a Processor

Patent #:	NONE	Issue Dt:		Application #:	14548041	Filing Dt:	11/19/2014
Publication #:	US20150154022	Pub Dt:	06/04/2015
Title:	Soft-Partitioning of a Register File Cache

Patent #:	9870225	Issue Dt:	01/16/2018	Application #:	14572186	Filing Dt:	12/16/2014
Publication #:	US20150178076	Pub Dt:	06/25/2015
Title:	PROCESSOR WITH VIRTUALIZED INSTRUCTION SET ARCHITECTURE & METHODS

Patent #:	10642501	Issue Dt:	05/05/2020	Application #:	14589693	Filing Dt:	01/05/2015
Title:	HARDWARE VIRTUALIZED INPUT OUTPUT MEMORY MANAGEMENT UNIT

Patent #:	9652240	Issue Dt:	05/16/2017	Application #:	14596407	Filing Dt:	01/14/2015
Publication #:	US20150205611	Pub Dt:	07/23/2015
Title:	STACK POINTER VALUE PREDICTION

Patent #:	9934039	Issue Dt:	04/03/2018	Application #:	14598415	Filing Dt:	01/16/2015
Publication #:	US20150205612	Pub Dt:	07/23/2015
Title:	Stack Saved Variable Pointer Value Prediction

Patent #:	9361242	Issue Dt:	06/07/2016	Application #:	14608630	Filing Dt:	01/29/2015
Publication #:	US20150220450	Pub Dt:	08/06/2015
Title:	Return Stack Buffer Having Multiple Address Slots Per Stack Entry

Patent #:	9424203	Issue Dt:	08/23/2016	Application #:	14608745	Filing Dt:	01/29/2015
Publication #:	US20150220451	Pub Dt:	08/06/2015
Title:	Storing Look-Up Table Indexes in a Return Stack Buffer

Patent #:	NONE	Issue Dt:		Application #:	14612069	Filing Dt:	02/02/2015
Publication #:	US20150227371	Pub Dt:	08/13/2015
Title:	Processors with Support for Compact Branch Instructions & Methods

Patent #:	NONE	Issue Dt:		Application #:	14612077	Filing Dt:	02/02/2015
Publication #:	US20150227366	Pub Dt:	08/13/2015
Title:	PROCESSOR WITH GRANULAR ADD IMMEDIATES CAPABILITY & METHODS

Patent #:	9740557	Issue Dt:	08/22/2017	Application #:	14612084	Filing Dt:	02/02/2015
Publication #:	US20150242274	Pub Dt:	08/27/2015
Title:	PIPELINED ECC-PROTECTED MEMORY ACCESS

Patent #:	10671391	Issue Dt:	06/02/2020	Application #:	14612090	Filing Dt:	02/02/2015
Publication #:	US20150242212	Pub Dt:	08/27/2015
Title:	MODELESS INSTRUCTION EXECUTION WITH 64/32-BIT ADDRESSING

Patent #:	10768930	Issue Dt:	09/08/2020	Application #:	14612104	Filing Dt:	02/02/2015
Publication #:	US20150227365	Pub Dt:	08/13/2015
Title:	PROCESSOR SUPPORTING ARITHMETIC INSTRUCTIONS WITH BRANCH ON OVERFLOW & METHODS

Patent #:	9727380	Issue Dt:	08/08/2017	Application #:	14625895	Filing Dt:	02/19/2015
Publication #:	US20150160981	Pub Dt:	06/11/2015
Title:	Global Register Protection In A Multi-Threaded Processor

Patent #:	9830275	Issue Dt:	11/28/2017	Application #:	14715117	Filing Dt:	05/18/2015
Publication #:	US20160342523	Pub Dt:	11/24/2016
Title:	TRANSLATION LOOKASIDE BUFFER

Patent #:	9898293	Issue Dt:	02/20/2018	Application #:	14722292	Filing Dt:	05/27/2015
Publication #:	US20150347144	Pub Dt:	12/03/2015
Title:	Decoding Instructions That Are Modified By One Or More Other Instructions

Patent #:	10423417	Issue Dt:	09/24/2019	Application #:	14741738	Filing Dt:	06/17/2015
Publication #:	US20160321078	Pub Dt:	11/03/2016
Title:	Fault Tolerant Processor for Real-Time Systems

Patent #:	9606834	Issue Dt:	03/28/2017	Application #:	14754436	Filing Dt:	06/29/2015
Publication #:	US20150301863	Pub Dt:	10/22/2015
Title:	ALLOCATING RESOURCES TO THREADS BASED ON SPECULATION METRIC

Patent #:	9703709	Issue Dt:	07/11/2017	Application #:	14791699	Filing Dt:	07/06/2015
Publication #:	US20160034395	Pub Dt:	02/04/2016
Title:	Method and Apparatus for Ensuring Data Cache Coherency

Patent #:	10048967	Issue Dt:	08/14/2018	Application #:	14798841	Filing Dt:	07/14/2015
Publication #:	US20160011869	Pub Dt:	01/14/2016
Title:	PROCESSOR ARRANGED TO OPERATE AS A SINGLE-THREADED (NX)-BIT PROCESSOR AND AS AN N-THREADED X-BIT PROCESSOR IN DIFFERENT MODES OF OPERATION

Patent #:	10318304	Issue Dt:	06/11/2019	Application #:	14809187	Filing Dt:	07/25/2015
Publication #:	US20160026470	Pub Dt:	01/28/2016
Title:	Conditional Branch Prediction Using a Long History

Patent #:	10108548	Issue Dt:	10/23/2018	Application #:	14829458	Filing Dt:	08/18/2015
Publication #:	US20160055083	Pub Dt:	02/25/2016
Title:	PROCESSORS AND METHODS FOR CACHE SPARING STORES

Patent #:	9672039	Issue Dt:	06/06/2017	Application #:	14842983	Filing Dt:	09/02/2015
Publication #:	US20160253175	Pub Dt:	09/01/2016
Title:	Register File Having a Plurality of Sub-Register Files

Patent #:	10318172	Issue Dt:	06/11/2019	Application #:	14873027	Filing Dt:	10/01/2015
Publication #:	US20160299700	Pub Dt:	10/13/2016
Title:	Cache Operation in a Multi-Threaded Processor

Patent #:	NONE	Issue Dt:		Application #:	14919922	Filing Dt:	10/22/2015
Publication #:	US20160117250	Pub Dt:	04/28/2016
Title:	Apparatus and Method of Throttling Hardware Pre-fetch

Patent #:	NONE	Issue Dt:		Application #:	14930740	Filing Dt:	11/03/2015
Publication #:	US20170123792	Pub Dt:	05/04/2017
Title:	Processors Supporting Endian Agnostic SIMD Instructions and Methods

Patent #:	10360038	Issue Dt:	07/23/2019	Application #:	14930913	Filing Dt:	11/03/2015
Publication #:	US20160055002	Pub Dt:	02/25/2016
Title:	METHOD AND APPARATUS FOR SCHEDULING THE ISSUE OF INSTRUCTIONS IN A MULTITHREADED PROCESSOR

Patent #:	10664280	Issue Dt:	05/26/2020	Application #:	14935579	Filing Dt:	11/09/2015
Publication #:	US20170132009	Pub Dt:	05/11/2017
Title:	Fetch Ahead Branch Target Buffer

Patent #:	10459725	Issue Dt:	10/29/2019	Application #:	15001628	Filing Dt:	01/20/2016
Publication #:	US20170206086	Pub Dt:	07/20/2017
Title:	Execution of Load Instructions in a Processor

Patent #:	NONE	Issue Dt:		Application #:	15079784	Filing Dt:	03/24/2016
Publication #:	US20170277539	Pub Dt:	09/28/2017
Title:	EXCEPTION HANDLING IN PROCESSOR USING BRANCH DELAY SLOT INSTRUCTION SET ARCHITECTURE

Patent #:	NONE	Issue Dt:		Application #:	15092728	Filing Dt:	04/07/2016
Publication #:	US20170293646	Pub Dt:	10/12/2017
Title:	APPARATUS AND METHODS FOR OUT OF ORDER ITEM SELECTION AND STATUS UPDATING

Patent #:	10649773	Issue Dt:	05/12/2020	Application #:	15092915	Filing Dt:	04/07/2016
Publication #:	US20170293486	Pub Dt:	10/12/2017
Title:	PROCESSORS SUPPORTING ATOMIC WRITES TO MULTIWORD MEMORY LOCATIONS & METHODS

Patent #:	NONE	Issue Dt:		Application #:	15093404	Filing Dt:	04/07/2016
Publication #:	US20170293556	Pub Dt:	10/12/2017
Title:	READ DISCARDS IN A PROCESSOR SYSTEM WITH WRITE-BACK CACHES

Patent #:	9870228	Issue Dt:	01/16/2018	Application #:	15134510	Filing Dt:	04/21/2016
Publication #:	US20160232007	Pub Dt:	08/11/2016
Title:	Prioritising of Instruction Fetching in Microprocessor Systems

Patent #:	9740454	Issue Dt:	08/22/2017	Application #:	15150177	Filing Dt:	05/09/2016
Publication #:	US20160253151	Pub Dt:	09/01/2016
Title:	CROSSING PIPELINED DATA BETWEEN CIRCUITRY IN DIFFERENT CLOCK DOMAINS

Patent #:	9910672	Issue Dt:	03/06/2018	Application #:	15183365	Filing Dt:	06/15/2016
Publication #:	US20160291976	Pub Dt:	10/06/2016
Title:	SPECULATIVE LOAD ISSUE

Patent #:	NONE	Issue Dt:		Application #:	15205445	Filing Dt:	07/08/2016
Publication #:	US20170010819	Pub Dt:	01/12/2017
Title:	CHECK POINTING A SHIFT REGISTER

Patent #:	10025527	Issue Dt:	07/17/2018	Application #:	15205555	Filing Dt:	07/08/2016
Publication #:	US20170010820	Pub Dt:	01/12/2017
Title:	CHECK POINTING A SHIFT REGISTER USING A CIRCULAR BUFFER

Patent #:	10360037	Issue Dt:	07/23/2019	Application #:	15281661	Filing Dt:	09/30/2016
Publication #:	US20170090933	Pub Dt:	03/30/2017
Title:	FETCH UNIT FOR PREDICTING TARGET FOR SUBROUTINE RETURN INSTRUCTIONS

Patent #:	10001997	Issue Dt:	06/19/2018	Application #:	15387394	Filing Dt:	12/21/2016
Publication #:	US20170102949	Pub Dt:	04/13/2017
Title:	PRIORITIZING INSTRUCTIONS BASED ON TYPE

Patent #:	9858194	Issue Dt:	01/02/2018	Application #:	15438000	Filing Dt:	02/21/2017
Publication #:	US20170168949	Pub Dt:	06/15/2017
Title:	Migration of Data to Register File Cache

Patent #:	10318296	Issue Dt:	06/11/2019	Application #:	15467073	Filing Dt:	03/23/2017
Publication #:	US20170192779	Pub Dt:	07/06/2017
Title:	SCHEDULING EXECUTION OF INSTRUCTIONS ON A PROCESSOR HAVING MULTIPLE HARDWARE THREADS WITH DIFFERENT EXECUTION RESOURCES

Patent #:	10754778	Issue Dt:	08/25/2020	Application #:	15488649	Filing Dt:	04/17/2017
Publication #:	US20170220471	Pub Dt:	08/03/2017
Title:	Control of Pre-Fetch Traffic

Patent #:	NONE	Issue Dt:		Application #:	15489975	Filing Dt:	04/18/2017
Publication #:	US20170220353	Pub Dt:	08/03/2017
Title:	STACK POINTER VALUE PREDICTION

Patent #:	10372453	Issue Dt:	08/06/2019	Application #:	15624121	Filing Dt:	06/15/2017
Publication #:	US20170364357	Pub Dt:	12/21/2017
Title:	Fetching Instructions in an Instruction Fetch Unit

Patent #:	NONE	Issue Dt:		Application #:	15633988	Filing Dt:	06/27/2017
Publication #:	US20170373836	Pub Dt:	12/28/2017
Title:	AES Hardware Implementation

Patent #:	10261798	Issue Dt:	04/16/2019	Application #:	15707059	Filing Dt:	09/18/2017
Publication #:	US20180004529	Pub Dt:	01/04/2018
Title:	INDIRECT BRANCH PREDICTION

Assignor

HELLOSOFT LIMITED

Exec Dt:

11/08/2017

Assignee

MIPS TECH LIMITED

IMAGINATION HOUSE

HOME PARK ESTATE

KINGS LANGLEY, UNITED KINGDOM WD4 8LZ

Correspondence name and address
	VORYS, SATER, SEYMOUR AND PEASE LLP
	1909 K STREET, N.W.
	9TH FLOOR
	WASHINGTON, DC 20006

Search Results as of: 06/18/2024 04:31 PM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6