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Patent Assignment Details
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Reel/Frame:040103/0925   Pages: 4
Recorded: 10/24/2016
Attorney Dkt #:1026-RT-6-IDT
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14
1
Patent #:
Issue Dt:
04/24/2001
Application #:
09587930
Filing Dt:
06/06/2000
Title:
Memory devices having a restore start address counter
2
Patent #:
Issue Dt:
12/16/2003
Application #:
10094101
Filing Dt:
03/08/2002
Title:
APPARATUS AND METHOD FOR GENERATING A COMPENSATED PERCENT-OF-CLOCK PERIOD DELAY SIGNAL
3
Patent #:
Issue Dt:
03/08/2005
Application #:
10107503
Filing Dt:
03/27/2002
Title:
APPARATUS AND METHOD FOR TRANSFERRING MULTI-BYTE WORDS IN A FLY-BY DMA OPERATION
4
Patent #:
Issue Dt:
08/10/2004
Application #:
10177382
Filing Dt:
06/21/2002
Title:
METHOD AND APPARATUS FOR REDUCING LATENCY DUE TO SET UP TIME BETWEEN DMA TRANSFERS
5
Patent #:
Issue Dt:
09/08/2009
Application #:
10222543
Filing Dt:
08/16/2002
Title:
METHOD AND APPARATUS FOR GENERATING A RANDOM BIT STREAM IN TRUE RANDOM NUMBER GENERATOR FASHION
6
Patent #:
Issue Dt:
03/15/2005
Application #:
10621055
Filing Dt:
07/15/2003
Title:
CLOCK PROCESSING LOGIC AND METHOD FOR DETERMINING CLOCK SIGNAL CHARACTERISTICS IN REFERENCE VOLTAGE AND TEMPERATURE VARYING ENVIRONMENTS
7
Patent #:
Issue Dt:
02/15/2005
Application #:
10643208
Filing Dt:
08/18/2003
Title:
INTEGRATED CIRCUIT DEVICES HAVING HIGH PRECISION DIGITAL DELAY LINES THEREIN
8
Patent #:
Issue Dt:
06/10/2008
Application #:
10788943
Filing Dt:
02/26/2004
Title:
MEMORY UNIT WITH CONTROLLER MANAGING MEMORY ACCESS THROUGH JTAG AND CPU INTERFACES
9
Patent #:
Issue Dt:
04/22/2008
Application #:
10808253
Filing Dt:
03/23/2004
Title:
COLLISION DETECTION IN A MULTI-PORT MEMORY SYSTEM
10
Patent #:
Issue Dt:
09/13/2005
Application #:
10880893
Filing Dt:
06/30/2004
Title:
INTEGRATED CIRCUIT DEVICES HAVING HIGH PRECISION DIGITAL DELAY LINES THEREIN
11
Patent #:
Issue Dt:
06/13/2006
Application #:
11042395
Filing Dt:
01/25/2005
Title:
CLOCK PROCESSING LOGIC AND METHOD FOR DETERMINING CLOCK SIGNAL CHARACTERISTICS IN REFERENCE VOLTAGE AND TEMPERATURE VARYING ENVIRONMENTS
12
Patent #:
Issue Dt:
04/10/2007
Application #:
11134899
Filing Dt:
05/23/2005
Publication #:
Pub Dt:
09/22/2005
Title:
INTEGRATED CIRCUIT SYSTEMS AND DEVICES HAVING HIGH PRECISION DIGITAL DELAY LINES THEREIN
13
Patent #:
Issue Dt:
04/15/2008
Application #:
11222390
Filing Dt:
09/08/2005
Title:
REDUCED SIZE DUAL-PORT SRAM CELL
14
Patent #:
Issue Dt:
05/04/2010
Application #:
11863164
Filing Dt:
09/27/2007
Publication #:
Pub Dt:
04/02/2009
Title:
SYNCHRONOUS ADDRESS AND DATA MULTIPLEXED MODE FOR SRAM
Assignor
1
Exec Dt:
10/05/2016
Assignee
1
2091, GYEONGCHUNG-DAERO, BUBAL-EUB, ICHEON-SI
GYEONGGI-DO, KOREA, REPUBLIC OF
Correspondence name and address
IP&T GROUP LLP
8230 LEESBURG PIKE
SUITE 650
VIENNA, VA 22182

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