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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	017586/0927			Pages:	7
		Recorded:	05/08/2006
Attorney Dkt #:	23748-01000
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 16

Patent #:	6574788	Issue Dt:	06/03/2003	Application #:	09712418	Filing Dt:	11/13/2000
Title:	METHOD AND SYSTEM FOR AUTOMATICALLY GENERATING LOW LEVEL PROGRAM COMMANDS AS DEPENDENCY GRAPHS FROM HIGH LEVEL PHYSICAL DESIGN STAGES

Patent #:	6557153	Issue Dt:	04/29/2003	Application #:	09714296	Filing Dt:	11/15/2000
Title:	METHOD AND SYSTEM FOR IMPLEMENTING A USER INTERFACE FOR PERFORMING PHYSICAL DESIGN OPERATIONS ON AN INTEGRATED CIRCUIT NETLIST

Patent #:	6857116	Issue Dt:	02/15/2005	Application #:	09714722	Filing Dt:	11/15/2000
Title:	OPTIMIZATION OF ABUTTED-PIN HIERARCHICAL PHYSICAL DESIGN

Patent #:	6553554	Issue Dt:	04/22/2003	Application #:	09908957	Filing Dt:	07/18/2001
Title:	METHOD AND SYSTEM FOR IMPLEMENTING A GRAPHICAL USER INTERFACE FOR DEPICTING LOOSE FLY LINE INTERCONNECTIONS BETWEEN MULTIPLE BLOCKS OF AN INTEGRATED CIRCUIT NETLIST

Patent #:	6564363	Issue Dt:	05/13/2003	Application #:	09909050	Filing Dt:	07/18/2001
Title:	METHOD AND SYSTEM FOR IMPLEMENTING A GRAPHICAL USER INTERFACE FOR DEFINING AND LINKING MULTIPLE ATTACH POINTS FOR MULTIPLE BLOCKS OF AN INTEGRATED CIRCUIT NETLIST

Patent #:	6564364	Issue Dt:	05/13/2003	Application #:	09909354	Filing Dt:	07/18/2001
Title:	METHOD AND SYSTEM FOR MAINTAINING ELEMENT ABSTRACTS OF AN INTEGRATED CIRCUIT NETLIST USING A MASTER LIBRARY FILE AND MODIFIABLE MASTER LIBRARY FILE

Patent #:	6757874	Issue Dt:	06/29/2004	Application #:	10104786	Filing Dt:	03/22/2002
Title:	FACILITATING VERIFICATION IN ABUTTED-PIN HIERARCHICAL PHYSICAL DESIGN

Patent #:	6854093	Issue Dt:	02/08/2005	Application #:	10104813	Filing Dt:	03/22/2002
Title:	FACILITATING PRESS OPERATION IN ABUTTED-PIN HIERARCHICAL PHYSICAL DESIGN

Patent #:	6865721	Issue Dt:	03/08/2005	Application #:	10104960	Filing Dt:	03/22/2002
Title:	OPTIMIZATION OF THE TOP LEVEL IN ABUTTED-PIN HEIRARCHICAL PHYSICAL DESIGN

Patent #:	6734046	Issue Dt:	05/11/2004	Application #:	10264679	Filing Dt:	10/03/2002
Title:	METHOD OF CUSTOMIZING AND USING MAPS IN GENERATING THE PADRING LAYOUT DESIGN

Patent #:	6823501	Issue Dt:	11/23/2004	Application #:	10264680	Filing Dt:	10/03/2002
Title:	METHOD OF GENERATING THE PADRING LAYOUT DESIGN USING AUTOMATION

Patent #:	7117469	Issue Dt:	10/03/2006	Application #:	10264691	Filing Dt:	10/03/2002
Title:	METHOD OF OPTIMIZING PLACEMENT AND ROUTING OF EDGE LOGIC IN PADRING LAYOUT DESIGN

Patent #:	7155693	Issue Dt:	12/26/2006	Application #:	10831700	Filing Dt:	04/23/2004
Title:	FLOORPLANNING A HIERARCHICAL PHYSICAL DESIGN TO IMPROVE PLACEMENT AND ROUTING

Patent #:	7185305	Issue Dt:	02/27/2007	Application #:	10855539	Filing Dt:	05/26/2004
Title:	CREATING A POWER DISTRIBUTION ARRANGEMENT WITH TAPERED METAL WIRES FOR A PHYSICAL DESIGN

Patent #:	7114142	Issue Dt:	09/26/2006	Application #:	10855667	Filing Dt:	05/26/2004
Title:	OPTIMIZING LOCATIONS OF PINS FOR BLOCKS IN A HIERARCHICAL PHYSICAL DESIGN BY USING PHYSICAL DESIGN INFORMATION OF A PRIOR HIERARCHICAL PHYSICAL DESIGN

Patent #:	7353488	Issue Dt:	04/01/2008	Application #:	10856268	Filing Dt:	05/27/2004
Title:	FLOW DEFINITION LANGUAGE FOR DESIGNING INTEGRATED CIRCUIT IMPLEMENTATION FLOWS

Assignor

Exec Dt:

03/09/2006

Assignee

5460 BAYFRONT PLAZA

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	RAJIV P. PATEL
	FENWICK & WEST LLP
	SILICON VALLEY CENTER
	801 CALIFORNIA STREET
	MOUNTAIN VIEW, CA 94041

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