skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:020360/0930   Pages: 8
Recorded: 01/14/2008
Attorney Dkt #:QIM 2007 VJ 34209 US
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
11877558
Filing Dt:
10/23/2007
Publication #:
Pub Dt:
04/23/2009
Title:
Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Memory Module
Assignors
1
Exec Dt:
11/13/2007
2
Exec Dt:
11/09/2007
3
Exec Dt:
11/30/2007
Assignees
1
GUSTAV-HEINEMANN-RING 212
MUNICH, GERMANY 81739
2
224 BLD. JOHN KENNEDY
CORBEIL ESSONNES CEDEX, FRANCE ZIP 31 P 91105
Correspondence name and address
SLATER & MATSIL, L.L.P
17950 PRESTON RD.
SUITE 1000
DALLAS, TX 75252

Search Results as of: 05/23/2024 04:24 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT