Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 015117/0933 | |
| Pages: | 4 |
| | Recorded: | 09/10/2004 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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08/22/2006
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Application #:
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10086665
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Filing Dt:
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02/28/2002
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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ON-CHIP INTER-SUBSYSTEM COMMUNICATION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10086938
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Filing Dt:
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02/28/2002
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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Multi-service system-on-chip including on-chip memory with multiple access path
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Patent #:
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Issue Dt:
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10/14/2008
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Application #:
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10469467
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Filing Dt:
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04/05/2004
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Publication #:
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Pub Dt:
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11/24/2005
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Title:
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SECURITY SYSTEM WITH AN INTELLIGENT DMA CONTROLLER
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Patent #:
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Issue Dt:
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01/26/2010
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Application #:
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10469529
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Filing Dt:
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08/28/2003
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Publication #:
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Pub Dt:
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09/23/2004
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Title:
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SUBSYSTEM BOOT AND PERIPHERAL DATA TRANSFER ARCHITECTURE FOR A SUBSYSTEM OF A SYSTEM-ON- CHIP
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Assignee
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| 2610 AUGUSTINE DRIVE |
| SANTA CLARA, CALIFORNIA 95054 |
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Correspondence name and address
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MORRISON & FOERSTER LLP
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SHANTANU BASU
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755 PAGE MILL ROAD
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PALO ALTO, CA 94304-1018
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