Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 034093/0933 | |
| Pages: | 5 |
| | Recorded: | 11/03/2014 | | |
Attorney Dkt #: | RA207.C1C1C3C1C2.B21 +7 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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05/29/2007
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Application #:
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10732533
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Filing Dt:
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12/11/2003
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Publication #:
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Pub Dt:
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09/02/2004
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Title:
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METHOD AND APPARATUS FOR COORDINATING MEMORY OPERATIONS AMONG DIVERSELY-LOCATED MEMORY COMPONENTS
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Patent #:
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Issue Dt:
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04/24/2007
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Application #:
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11094137
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Filing Dt:
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03/31/2005
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Publication #:
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Pub Dt:
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08/04/2005
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Title:
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MEMORY DEVICE WITH CLOCK MULTIPLIER CIRCUIT
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Patent #:
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Issue Dt:
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03/05/2013
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Application #:
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11280560
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Filing Dt:
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11/15/2005
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Publication #:
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Pub Dt:
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04/13/2006
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Title:
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MEMORY MODULE WITH TERMINATION COMPONENT
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Patent #:
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Issue Dt:
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06/11/2013
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Application #:
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12111816
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Filing Dt:
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04/29/2008
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Publication #:
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Pub Dt:
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03/05/2009
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Title:
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MEMORY MODULE WITH TERMINATION COMPONENT
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Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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13543779
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Filing Dt:
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07/06/2012
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Publication #:
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Pub Dt:
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11/15/2012
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Title:
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MEMORY CONTROLLER WITH SELECTIVE DATA TRANSMISSION DELAY
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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13899844
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Filing Dt:
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05/22/2013
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Publication #:
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Pub Dt:
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09/26/2013
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Title:
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MEMORY MODULE
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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14104188
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Filing Dt:
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12/12/2013
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Publication #:
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Pub Dt:
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04/10/2014
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Title:
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MEMORY CONTROLLER THAT ENFORCES STROBE-TO-STROBE TIMING OFFSET
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Patent #:
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Issue Dt:
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04/12/2016
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Application #:
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14523922
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Filing Dt:
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10/26/2014
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Publication #:
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Pub Dt:
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02/12/2015
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Title:
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MEMORY MODULE
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Assignee
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1050 ENTERPRISE WAY, SUITE 700 |
SUNNYVALE, CALIFORNIA 94089 |
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Correspondence name and address
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TARISA WAIN
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1050 ENTERPRISE WAY #700
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SUNNYVALE, CA 94089
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