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Patent Assignment Details
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Reel/Frame:034093/0933   Pages: 5
Recorded: 11/03/2014
Attorney Dkt #:RA207.C1C1C3C1C2.B21 +7
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8
1
Patent #:
Issue Dt:
05/29/2007
Application #:
10732533
Filing Dt:
12/11/2003
Publication #:
Pub Dt:
09/02/2004
Title:
METHOD AND APPARATUS FOR COORDINATING MEMORY OPERATIONS AMONG DIVERSELY-LOCATED MEMORY COMPONENTS
2
Patent #:
Issue Dt:
04/24/2007
Application #:
11094137
Filing Dt:
03/31/2005
Publication #:
Pub Dt:
08/04/2005
Title:
MEMORY DEVICE WITH CLOCK MULTIPLIER CIRCUIT
3
Patent #:
Issue Dt:
03/05/2013
Application #:
11280560
Filing Dt:
11/15/2005
Publication #:
Pub Dt:
04/13/2006
Title:
MEMORY MODULE WITH TERMINATION COMPONENT
4
Patent #:
Issue Dt:
06/11/2013
Application #:
12111816
Filing Dt:
04/29/2008
Publication #:
Pub Dt:
03/05/2009
Title:
MEMORY MODULE WITH TERMINATION COMPONENT
5
Patent #:
Issue Dt:
09/17/2013
Application #:
13543779
Filing Dt:
07/06/2012
Publication #:
Pub Dt:
11/15/2012
Title:
MEMORY CONTROLLER WITH SELECTIVE DATA TRANSMISSION DELAY
6
Patent #:
Issue Dt:
05/06/2014
Application #:
13899844
Filing Dt:
05/22/2013
Publication #:
Pub Dt:
09/26/2013
Title:
MEMORY MODULE
7
Patent #:
Issue Dt:
06/09/2015
Application #:
14104188
Filing Dt:
12/12/2013
Publication #:
Pub Dt:
04/10/2014
Title:
MEMORY CONTROLLER THAT ENFORCES STROBE-TO-STROBE TIMING OFFSET
8
Patent #:
Issue Dt:
04/12/2016
Application #:
14523922
Filing Dt:
10/26/2014
Publication #:
Pub Dt:
02/12/2015
Title:
MEMORY MODULE
Assignors
1
Exec Dt:
04/24/2001
2
Exec Dt:
04/24/2001
3
Exec Dt:
04/24/2001
4
Exec Dt:
04/24/2001
Assignee
1
1050 ENTERPRISE WAY, SUITE 700
SUNNYVALE, CALIFORNIA 94089
Correspondence name and address
TARISA WAIN
1050 ENTERPRISE WAY #700
SUNNYVALE, CA 94089

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