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Reel/Frame:061368/0947   Pages: 6
Recorded: 10/10/2022
Attorney Dkt #:INTELTECH CA ULC TO INTEL
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
5537341
Issue Dt:
07/16/1996
Application #:
08387402
Filing Dt:
02/10/1995
Title:
COMPLEMENTARY ARCHITECTURE FOR FIELD-PROGRAMMABLE GATE ARRAYS
2
Patent #:
6631510
Issue Dt:
10/07/2003
Application #:
09429013
Filing Dt:
10/29/1999
Title:
AUTOMATIC GENERATION OF PROGRAMMABLE LOGIC DEVICE ARCHITECTURES
3
Patent #:
6590419
Issue Dt:
07/08/2003
Application #:
09478097
Filing Dt:
10/12/1999
Title:
HETEROGENEOUS INTERCONNECTION ARCHITECTURE FOR PROGRAMMABLE LOGIC DEVICES
4
Patent #:
6828824
Issue Dt:
12/07/2004
Application #:
10449753
Filing Dt:
05/30/2003
Publication #:
US20040017222
Pub Dt:
01/29/2004
Title:
HETEROGENEOUS INTERCONNECTION ARCHITECTURE FOR PROGRAMMABLE LOGIC DEVICES
5
Patent #:
7051313
Issue Dt:
05/23/2006
Application #:
10641193
Filing Dt:
08/13/2003
Title:
AUTOMATIC GENERATION OF PROGRAMMABLE LOGIC DEVICE ARCHITECTURES
6
Patent #:
7546494
Issue Dt:
06/09/2009
Application #:
11462151
Filing Dt:
08/03/2006
Publication #:
US20080031311
Pub Dt:
02/07/2008
Title:
SKEW-CORRECTING APPARATUS USING DUAL LOOPBACK
7
Patent #:
7536579
Issue Dt:
05/19/2009
Application #:
11462157
Filing Dt:
08/03/2006
Publication #:
US20080031312
Pub Dt:
02/07/2008
Title:
SKEW-CORRECTING APPARATUS USING ITERATIVE APPROACH
8
Patent #:
7760836
Issue Dt:
07/20/2010
Application #:
11462164
Filing Dt:
08/03/2006
Publication #:
US20080126888
Pub Dt:
05/29/2008
Title:
SKEW-CORRECTING APPARATUS USING EXTERNAL COMMUNICATIONS ELEMENT
9
Patent #:
7924938
Issue Dt:
04/12/2011
Application #:
11902532
Filing Dt:
09/24/2007
Publication #:
US20090080564
Pub Dt:
03/26/2009
Title:
CONTEXT-SENSITIVE OVERHEAD PROCESSOR
10
Patent #:
8136020
Issue Dt:
03/13/2012
Application #:
11987300
Filing Dt:
11/29/2007
Publication #:
US20090077448
Pub Dt:
03/19/2009
Title:
FORWARD ERROR CORRECTION CODEC
11
Patent #:
8238349
Issue Dt:
08/07/2012
Application #:
12141157
Filing Dt:
06/18/2008
Publication #:
US20090319729
Pub Dt:
12/24/2009
Title:
METHOD OF ACCESSING STORED INFORMATION IN MULTI-FRAMED DATA TRANSMISSIONS.
12
Patent #:
NONE
Issue Dt:
Application #:
12431781
Filing Dt:
04/29/2009
Publication #:
US20100217960
Pub Dt:
08/26/2010
Title:
Method of Performing Serial Functions in Parallel
13
Patent #:
8745113
Issue Dt:
06/03/2014
Application #:
12458122
Filing Dt:
07/01/2009
Publication #:
US20100287224
Pub Dt:
11/11/2010
Title:
Pseudo-random bit sequence generator
14
Patent #:
8199782
Issue Dt:
06/12/2012
Application #:
12488836
Filing Dt:
06/22/2009
Publication #:
US20100215060
Pub Dt:
08/26/2010
Title:
METHOD OF MULTIPLE LANE DISTRIBUTION (MLD) DESKEW
15
Patent #:
8254378
Issue Dt:
08/28/2012
Application #:
12554043
Filing Dt:
09/04/2009
Publication #:
US20110019666
Pub Dt:
01/27/2011
Title:
STRICT-SENSE MINIMAL SPANNING SWITCH NON-BLOCKING ARCHITECTURE
16
Patent #:
8498370
Issue Dt:
07/30/2013
Application #:
12636947
Filing Dt:
12/14/2009
Publication #:
US20110096882
Pub Dt:
04/28/2011
Title:
METHOD AND APPARATUS FOR DESKEWING DATA TRANSMISSIONS
17
Patent #:
9043685
Issue Dt:
05/26/2015
Application #:
12656631
Filing Dt:
02/05/2010
Publication #:
US20110197111
Pub Dt:
08/11/2011
Title:
Method and apparatus for error-correction in and processing of GFP-T superblocks
18
Patent #:
8359518
Issue Dt:
01/22/2013
Application #:
12702659
Filing Dt:
02/09/2010
Publication #:
US20110099452
Pub Dt:
04/28/2011
Title:
2D PRODUCT CODE AND METHOD FOR DETECTING FALSE DECODING ERRORS
19
Patent #:
8631171
Issue Dt:
01/14/2014
Application #:
12805923
Filing Dt:
08/25/2010
Publication #:
US20120054388
Pub Dt:
03/01/2012
Title:
Method for finding starting bit of reference frames for an alternating-parity reference channel
20
Patent #:
8413026
Issue Dt:
04/02/2013
Application #:
12954784
Filing Dt:
11/26/2010
Publication #:
US20120137194
Pub Dt:
05/31/2012
Title:
FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY
21
Patent #:
8385472
Issue Dt:
02/26/2013
Application #:
13084439
Filing Dt:
04/11/2011
Publication #:
US20110182581
Pub Dt:
07/28/2011
Title:
CONTEXT-SENSITIVE OVERHEAD PROCESSOR
22
Patent #:
8363684
Issue Dt:
01/29/2013
Application #:
13399673
Filing Dt:
02/17/2012
Publication #:
US20120147905
Pub Dt:
06/14/2012
Title:
METHOD OF MULTIPLE LANE DISTRIBUTION (MLD) DESKEW
23
Patent #:
9208117
Issue Dt:
12/08/2015
Application #:
13547697
Filing Dt:
07/12/2012
Publication #:
US20120275462
Pub Dt:
11/01/2012
Title:
METHOD OF ACCESSING STORED INFORMATION IN MULTI-FRAMED DATA TRANSMISSIONS
24
Patent #:
8477770
Issue Dt:
07/02/2013
Application #:
13555755
Filing Dt:
07/23/2012
Publication #:
US20120287927
Pub Dt:
11/15/2012
Title:
STRICT-SENSE MINIMAL SPANNING SWITCH NON-BLOCKING ARCHITECTURE
25
Patent #:
8560915
Issue Dt:
10/15/2013
Application #:
13712413
Filing Dt:
12/12/2012
Publication #:
US20130132794
Pub Dt:
05/23/2013
Title:
2D PRODUCT CODE AND METHOD FOR DETECTING FALSE DECODING ERRORS
26
Patent #:
8705581
Issue Dt:
04/22/2014
Application #:
13750377
Filing Dt:
01/25/2013
Title:
METHOD OF MULTIPLE LANE DISTRIBUTION (MLD) DESKEW
27
Patent #:
8923441
Issue Dt:
12/30/2014
Application #:
13774537
Filing Dt:
02/22/2013
Publication #:
US20130230055
Pub Dt:
09/05/2013
Title:
CONTEXT-SENSITIVE OVERHEAD PROCESSOR
28
Patent #:
8645771
Issue Dt:
02/04/2014
Application #:
13793826
Filing Dt:
03/11/2013
Publication #:
US20130191702
Pub Dt:
07/25/2013
Title:
FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY
29
Patent #:
9264381
Issue Dt:
02/16/2016
Application #:
13913342
Filing Dt:
06/07/2013
Publication #:
US20130272300
Pub Dt:
10/17/2013
Title:
STRICT-SENSE MINIMAL SPANNING SWITCH NON-BLOCKING ARCHITECTURE
30
Patent #:
8718215
Issue Dt:
05/06/2014
Application #:
13932637
Filing Dt:
07/01/2013
Publication #:
US20130294555
Pub Dt:
11/07/2013
Title:
METHOD AND APPARATUS FOR DESKEWING DATA TRANSMISSIONS
31
Patent #:
9092580
Issue Dt:
07/28/2015
Application #:
14105798
Filing Dt:
12/13/2013
Publication #:
US20140101350
Pub Dt:
04/10/2014
Title:
METHOD FOR FINDING STARTING BIT OF REFERENCE FRAMES FOR AN ALTERNATING-PARITY REFERENCE CHANNEL
32
Patent #:
9063872
Issue Dt:
06/23/2015
Application #:
14139402
Filing Dt:
12/23/2013
Publication #:
US20140189446
Pub Dt:
07/03/2014
Title:
FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY
33
Patent #:
9281911
Issue Dt:
03/08/2016
Application #:
14243725
Filing Dt:
04/02/2014
Title:
METHOD OF MULTIPLE LANE DISTRIBUTION (MLD) DESKEW
34
Patent #:
9619206
Issue Dt:
04/11/2017
Application #:
14259824
Filing Dt:
04/23/2014
Publication #:
US20140237013
Pub Dt:
08/21/2014
Title:
PSEUDO-RANDOM BIT SEQUENCE GENERATOR
35
Patent #:
9448885
Issue Dt:
09/20/2016
Application #:
14728588
Filing Dt:
06/02/2015
Publication #:
US20150261611
Pub Dt:
09/17/2015
Title:
FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY
Assignor
1
INTEL TECHNOLOGY OF CANADA, ULC
Exec Dt:
07/08/2022
Assignee
1
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
ANGELA MILLER
C/O CLARIVATE
P.O. BOX 5427
TUCSON, AZ 85703

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