Patent Assignment Details
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| Reel/Frame: | 022825/0951 | |
| Pages: | 8 |
| | Recorded: | 06/15/2009 | | |
| Conveyance: | CORRECTIVE TO CORRECT AN ERRORNEOUSLY RECORDED APPLICATION NUMBER 09/362319, RECORDED AT REEL 013343 FRAME 0351. THE ASSIGNOR HEREBY CONFIRMS THE MERGER. |
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Total properties:
6
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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08459570
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Filing Dt:
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06/02/1995
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Title:
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PROGRAMMABLE OPTIMIZED-DISTRIBUTION LOGIC ALLOCATOR FOR A HIGH-DENSITY COMPLEX PLD
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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08948306
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Filing Dt:
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10/09/1997
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Title:
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VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08995615
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Filing Dt:
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12/22/1997
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Title:
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PROGRAMMABLE INPUT/OUTPUT BLOCK (IOB) IN FPGA INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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09212331
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Filing Dt:
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12/15/1998
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Title:
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FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS EACH WITH STATICALLY AND DYNAMICALLY CONTROLLABLE READ MODE
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09217646
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Filing Dt:
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12/21/1998
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Title:
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METHOD OF FABRICATING PROGRAMMING AND ERASING A DUAL POCKET TWO
SIDED PROGRAM/ERASE NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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10090209
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Filing Dt:
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03/04/2002
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS
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Assignee
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| 5555 NE MOORE COURT |
| HILLSBORO, OREGON 97124-6421 |
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Correspondence name and address
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MARK L. BECKER
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5555 NE MOORE COURT
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HILLSBORO, OR 97124-6421
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