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Patent Assignment Details
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Reel/Frame:028011/0951   Pages: 3
Recorded: 04/09/2012
Conveyance: MERGER (SEE DOCUMENT FOR DETAILS).
Total properties: 12
1
Patent #:
Issue Dt:
11/18/2003
Application #:
10191888
Filing Dt:
07/08/2002
Title:
FIELD PROGRAMMABLE GATE ARRAY BASED UPON TRANSISTOR GATE OXIDE BREAKDOWN
2
Patent #:
Issue Dt:
08/02/2005
Application #:
10642370
Filing Dt:
08/15/2003
Publication #:
Pub Dt:
02/17/2005
Title:
FIELD PROGRAMMABLE GATE ARRAY
3
Patent #:
Issue Dt:
12/06/2005
Application #:
10782564
Filing Dt:
02/18/2004
Publication #:
Pub Dt:
08/04/2005
Title:
COMBINATION FIELD PROGRAMMABLE GATE ARRAY ALLOWING DYNAMIC REPROGRAMMABILITY AND NON-VOLATILE PROGRAMMABILITY BASED UPON TRANSISTOR GATE OXIDE BREAKDOWN
4
Patent #:
Issue Dt:
06/20/2006
Application #:
10857667
Filing Dt:
05/28/2004
Publication #:
Pub Dt:
08/04/2005
Title:
COMBINATION FIELD PROGRAMMABLE GATE ARRAY ALLOWING DYNAMIC REPROGRAMMABILITY
5
Patent #:
Issue Dt:
11/14/2006
Application #:
10944978
Filing Dt:
09/20/2004
Publication #:
Pub Dt:
03/23/2006
Title:
FIELD PROGRAMMABLE GATE ARRAYS USING BOTH VOLATILE AND NONVOLATILE MEMORY CELL PROPERTIES AND THEIR CONTROL
6
Patent #:
Issue Dt:
01/16/2007
Application #:
10974107
Filing Dt:
10/26/2004
Publication #:
Pub Dt:
12/15/2005
Title:
FIELD PROGRAMMABLE GATE ARRAY LOGIC UNIT AND ITS CLUSTER
7
Patent #:
Issue Dt:
03/20/2007
Application #:
11108927
Filing Dt:
04/18/2005
Publication #:
Pub Dt:
10/19/2006
Title:
FAST PROCESSING PATH USING FIELD PROGRAMMABLE GATE ARRAY LOGIC UNIT
8
Patent #:
Issue Dt:
12/20/2005
Application #:
11109966
Filing Dt:
04/19/2005
Publication #:
Pub Dt:
08/25/2005
Title:
FIELD PROGRAMMABLE GATE ARRAY
9
Patent #:
Issue Dt:
06/13/2006
Application #:
11252126
Filing Dt:
10/17/2005
Publication #:
Pub Dt:
02/16/2006
Title:
FIELD PROGRAMMABLE GATE ARRAY
10
Patent #:
Issue Dt:
10/02/2007
Application #:
11356805
Filing Dt:
02/17/2006
Publication #:
Pub Dt:
06/14/2007
Title:
MEMORY CELL COMPRISING AN OTP NONVOLATILE MEMORY UNIT AND A SRAM UNIT
11
Patent #:
Issue Dt:
08/12/2008
Application #:
11400924
Filing Dt:
04/10/2006
Publication #:
Pub Dt:
08/02/2007
Title:
PROGRAMMABLE LOGIC FUNCTION GENERATOR USING NON-VOLATILE PROGRAMMABLE MEMORY SWITCHES
12
Patent #:
Issue Dt:
11/20/2012
Application #:
13193984
Filing Dt:
07/29/2011
Title:
METHOD AND SYSTEM FOR PLACING INTEGRATED CIRCUITS INTO PREDOMINANTLY ULTRA-LOW VOLTAGE MODE FOR STANDBY PURPOSES
Assignor
1
Exec Dt:
04/02/2012
Assignee
1
2 CHURCH STREET
CLARENDON HOUSE
HAMILTON HM DX, BERMUDA
Correspondence name and address
MARK BECKER
5555 NE MOORE CT
HILLSBORO, OR 97124

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